A 225mW 28Gb/s SerDes in 40nm CMOS with 13dB of analog equalization for 100GBASE-LR4 and optical transport lane 4.4 applications

Harwood, M. G.; Nielsen, Steffen; Szczepanek, Andre; Allred, Richard; Batty, Sean; Case, Mike; Forey, Simon; Gopalakrishnan, Karthik; Kan, Larry; Killips, B.; Mishra, Parmanand; Pande, Rama; Rategh, H.R.; Ren, Alan; Sanders, J. W.; Schoy, A.; Ward, R.J.; Wetterhorn, Martin; Yeung, Norman

doi:10.1109/isscc.2012.6177032

Cited by 23 publications

(6 citation statements)

References 4 publications

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“…We can see that reference [8][9][10] have better technology with much higher characteristic frequency f T . With a structure of TX FFE + RX CTLE & DFE, reference [8] can compensate the highest channel loss at Nyquist frequency of 28 Gb/s data rate based on the advanced 32 nm SOI CMOS technology.…”

Section: Measurement Resultsmentioning

confidence: 83%

“…With a structure of TX FFE + RX CTLE & DFE, reference [8] can compensate the highest channel loss at Nyquist frequency of 28 Gb/s data rate based on the advanced 32 nm SOI CMOS technology. While [10] consumes the lowest power because of its simpler structure. On the other hand, our work can compensate larger loss compared with [9] and [10], and the processing speed is also the highest among all works.…”

Section: Measurement Resultsmentioning

confidence: 99%

“…While [10] consumes the lowest power because of its simpler structure. On the other hand, our work can compensate larger loss compared with [9] and [10], and the processing speed is also the highest among all works. Although the power consumption of our work is somewhat large, its adaption feature outperforms the others since both CTLE and DFE are all adaptive in our design.…”

Section: Measurement Resultsmentioning

confidence: 99%

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A 33 Gb/s combined adaptive CTLE and half-rate look-ahead DFE in 0.13 µm BiCMOS technology for serial link

Zhang

2018

IEICE Electron. Express

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Abstract:A 33 Gbit/s equalizer chip fabricated in 0.13 μm BiCMOS technology is presented. The proposed equalizer prototype includes adaptive continue time linear equalizer (CTLE) with middle frequency compensation and adaptive half-rate look ahead decision feedback equalizer (DFE). The slope detection based CTLE employs a two-path amplifier to adjust the ratio of the high frequency and low frequency adaptively, and a middle frequency amplifier dedicated to provide an appropriate compensation in the intermediate frequency range. For the half-rate DFE, by using a look ahead structure and an analog LMS algorithm circuit, the performance is improved in speed and area. Measurement results show that the equalizer chip can compensate lossy channel with a loss of 26 dB at 20 GHz effectively and the data rate can be up to 33 Gb/s under 3.3 V power supply, the total power consumption is about 726 mW at 33 Gb/s data rate.

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Section: Measurement Resultsmentioning

confidence: 83%

Section: Measurement Resultsmentioning

confidence: 99%

Section: Measurement Resultsmentioning

confidence: 99%

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A 33 Gb/s combined adaptive CTLE and half-rate look-ahead DFE in 0.13 µm BiCMOS technology for serial link

Zhang

2018

IEICE Electron. Express

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“…Because LDO is not placed in the DLL loop, high frequency supply-noise-rejection is achieved by introducing a low-frequency pole in the regulator's supply noise transfer function [4]. The LDO combines fast/slow paths [2] with a replica-load of 1:16 ratio to reduce area and power consumption (Fig. 2), which improves supply noise rejection and allow using small bypass capacitor (C D ) to suppress supply noise over a wide range of frequencies.…”

Section: Proposed Architecture and Implementationmentioning

confidence: 99%

“…This poses stringent requirements on the clock generation and distribution circuits to maximize the overall I/O performance. To push data rates to 25Gb/s and beyond, half-rate links with oversampled CDRs and quarter-rate architectures have been used [1][2], both of which require generating quadrature phases with low power and area. In [1], an LC-VCO followed by dividers generates half-rate clocks for both TX and RX in a 28Gb/s transceiver.…”

Section: Introductionmentioning

confidence: 99%

A 2GHz-to-7.5GHz quadrature clock-generator using digital delay locked loops for multi-standard I/Os in 14nm CMOS

Elshazly

Balankutty

Huang

et al. 2014

2014 Symposium on VLSI Circuits Digest of Technical Papers

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A highly digital quadrature clock generator using a digital DLL that employs a digital loop filter and digitally-calibrated replica-based regulator is presented. The proposed DLL combines the advantages of both analog and digital loop-filters of conventional architectures to implement a wide-range, energy efficient, highly digital, and high performance quadrature clock generator. To suppress supply-noise, we propose an LDO that combines fast/slow paths with a replica-load to achieve better than 20dB rejection with small area and low power. Fabricated in Intel's 14nm CMOS process, the proposed digital DLL operates over a wide range of output frequencies (2GHz-to-7.5GHz). At 7GHz, it achieves 176fs rms /2.7ps pp long-term jitter while consuming 4.4mW. The DLL is 4X smaller than state-of-the art designs and occupies an active area of 0.0024mm 2 .

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A 28-Gb/s 4.5-pJ/bit transceiver with 1-tap decision feedback equalizer in 28-nm CMOS

Miyaoka

Terasawa

Kudo

et al. 2015

2015 IEEE Asian Solid-State Circuits Conference (A-Sscc)

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A 225mW 28Gb/s SerDes in 40nm CMOS with 13dB of analog equalization for 100GBASE-LR4 and optical transport lane 4.4 applications

Cited by 23 publications

References 4 publications

A 33 Gb/s combined adaptive CTLE and half-rate look-ahead DFE in 0.13 µm BiCMOS technology for serial link

A 33 Gb/s combined adaptive CTLE and half-rate look-ahead DFE in 0.13 µm BiCMOS technology for serial link

A 2GHz-to-7.5GHz quadrature clock-generator using digital delay locked loops for multi-standard I/Os in 14nm CMOS

A 28-Gb/s 4.5-pJ/bit transceiver with 1-tap decision feedback equalizer in 28-nm CMOS

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