A 24-mW 28-Gb/s wireline receiver with low-frequency equalizing CTLE and 2-tap speculative DFE

This paper presents a wide rate range receiver including adaptive continuous time linear equalizer (CTLE) and loop-unrolled half rate decision feedback equalizer (DFE). A hybrid filter is adopted to expand the rate range of adaptive CTLE with spectrum balancing technology. The current-integrating summer is introduced to reduce the power of half-rate loop-unrolled DFE. The post-simulation is carried out by 0.18 μm CMOS TSMC technology and the results show that the rate range of adaptive CTLE can reach to 6.25-10 Gb/s. When the 10 Gb/s PRBS7 signal is transmitted through the 18-inch FR4 backplane with 15.451 dB loss at Nyquist frequency, the eye diagram is obviously open and its horizontal opening is about 0.9 UI.

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“…Summer is a key module that affects the performance and power of unrolled half rate DFE [25,26,27,28,29]. Fig.…”

Section: Current-integrating Summermentioning

confidence: 99%

6.25-10Gb/s adaptive CTLE with spectrum balancing and loop-unrolled half-rate DFE in TSMC 0.18µm CMOS

Sun

Zhang

Yang

2022

IEICE Electron. Express

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“…For data communication power, in particular, consumption is a very important factor in maintaining high performance. There are several previous studies of 28 Gbps or higher data rates [1][2][3][4][5]. Those use unrolled decision feedback equalizers to meet critical timing margins, but the unrolled CTLE structure increases the power and die's area.…”

Section: Introductionmentioning

confidence: 99%

“…The RX CTLE is similar to TX FFE CTLE except the input is an anal signal. The RX CTLE is often called a discrete-time linear equalizer [3,8]. As an FIR filt designed to subtract ISI effects from adjacent bits.…”

Section: Introductionmentioning

confidence: 99%

Receiver Analog Front-End Cascading Transimpedance Amplifier and Continuous-Time Linear Equalizer for Signals of 5 to 30 Gb/s

Naidu

2022

Electronics

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A 5–30 Gb/s receiver analog front-end (AFE) cascading transimpedance amplifier (TIA) and continuous-time linear equalizer (CTLE) were implemented using a Taiwan Semiconductor 180 nm process. The system comprises a two-stage differential input pair CTLE, TIA, and a differential termination resistor Rm. A source-degenerated transconductance stage was adopted in the CTLE, and source follower and shunt feedback resistor stages were adopted in the TIA. The proposed CTLE could achieve high frequencies by altering the tail current with fixed degenerate capacitance CS and resistance RS. The proposed AFE achieved high bandwidth, and the use of a feedback resistor Rf and inductor Lf improved its high-frequency performance. Simulation results revealed that the CTLE can compensate for 16 dB of channel loss at a 3 GHz Nyquist frequency and can open closed eyes in a 6 Gb/s non-return-to-zero signal with a bit error rate of 0.16 × 10−12 for a 231 − 1 pseudorandom binary sequence input. The AFE could compensate for 12 dB of channel loss at a 15 GHz Nyquist frequency and can open closed eyes in a 30 Gb/s PAM4 signal from a pseudorandom binary sequence input; it consumed 27 mW of power at 1.8 V.

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“…DFE can effectively eliminate inter-symbol interference caused by finite band, crosstalk, and reflection, but it is effective to eliminate the precursor [6,7,8,9]. Therefore, the combination of CTLE and DFE is widely used to eliminate inter-symbol interference at the receiver [10,11,12,13,14]. Because of temperature variation, material properties, length and bends, it is very important for equalizer to automatically detect and critically compensate for the high frequency loss of channel.…”

Section: Introductionmentioning

confidence: 99%

A 36 Gb/s wireline receiver with adaptive CTLE and 1-tap speculative DFE in 0.13 µm BiCMOS technology

Zhang

Yang

2020

IEICE Electron. Express

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This paper presents a 36 Gb/s receiver equalizer including an adaptive continuous time linear equalizer (CTLE), which is based on slope detection and a half-rate speculative decision feedback equalizer (DFE) in 0.13 µm BiCMOS technology for high speed serial link. The CTLE with middle frequency compensation can not only adjust the ratio of high frequency and low frequency components adaptively, but also provide a small amount of equalization to middle frequency range. A half-rate speculative DFE, which is connected to the back of the CTLE, can satisfy the time constraints and eliminate the residual intersymbol interference. The chip area including pads is about 1.2 mm 2 and the power consumption is about 750 mW under 3.3 V power supply. Measurement results show that the receiver chip can effectively equalize 24 dB loss at Nyquist frequency and a clear eye diagram can be captured at 36 Gb/s.

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A 24-mW 28-Gb/s wireline receiver with low-frequency equalizing CTLE and 2-tap speculative DFE

Cited by 10 publications

References 6 publications

6.25-10Gb/s adaptive CTLE with spectrum balancing and loop-unrolled half-rate DFE in TSMC 0.18µm CMOS

6.25-10Gb/s adaptive CTLE with spectrum balancing and loop-unrolled half-rate DFE in TSMC 0.18µm CMOS

Receiver Analog Front-End Cascading Transimpedance Amplifier and Continuous-Time Linear Equalizer for Signals of 5 to 30 Gb/s

A 36 Gb/s wireline receiver with adaptive CTLE and 1-tap speculative DFE in 0.13 µm BiCMOS technology

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