A 256 kb nonvolatile ferroelectric memory at 3 V and 100 ns

A survey of circuit innovations in ferroelectric random-access memories

“…One challenge is that only approxi- [27]. WL and RWL are raised simultaneously to access the memory cell on the left and the reference cell on the right of the column.…”

“…WL and RWL are raised simultaneously to access the memory cell on the left and the reference cell on the right of the column. WL and RWL are kept at 0 V (not shown) throughout the operation [27]. mate values of and are known in advance.…”

“…A reference capacitor always stores a "0," but it is sized larger than such that its projected signal on the BL, , is midway between and [24], [27]. The timing diagram used by Sumi et al [27] for a read operation is shown in Fig.…”

“…Adding a reset transistor to each reference cell, which was first introduced by Sumi et al [27], has an additional benefit: assume that the BL is driven to 0 V while BL is driven to by the sense amplifier. Just prior to deactivating the RWL , the voltage across is full , with the PL at and the BL at 0 V. By deactivating the RWL , one node of is still at , while the other node (the storage node) is floating.…”

“…Also, a BL//PL architecture could be power consuming if multiple platelines are activated to access multiple memory cells in the selected row. For larger arrays, the PL can be segmented into local platelines (LPL's) that run parallel to the WL and controlled by a global plateline (GPL) that runs parallel to the BL [27], [43]. As shown in Fig.…”