A 26 $\mu$W 8 bit 10 MS/s Asynchronous SAR ADC for Low Energy Radios

Harpe, Pieter; Zhou, Changjian; Bi, Yu; Meijs, N.P. van der; Wang, Xiaoyan; Philips, Kathleen; Dolmans, Guido; Groot, Harmke de

doi:10.1109/jssc.2011.2143870

Cited by 301 publications

(178 citation statements)

References 7 publications

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“…The DAC output vector (DAC out in Fig. 5) can be built evaluating (11) and (12) for all the possible vectors D depending on the switching algorithm. This behavioral model, which entails arithmetic operations on vectors, has been implemented in MATLAB.…”

Section: Cbw Modelmentioning

confidence: 99%

“…Unfortunately, such a procedure is extremely time-consuming and requires heavy data post-processing to estimate the static nonlinearity metrics as well as the Signal-to-Noise and Distortion Ratio (SNDR) and the Equivalent Number of Bits (ENoB). Similar issues arise also in many ultra-low-power designs where sub-10fF unit capacitors are adopted [16,10,11]. In this case, the impact of the DAC parasitics on the converter power consumption becomes not negligible and in a traditional EDA tool environment its estimate always relies on transient analyses, thus being time-consuming.…”

Section: Introductionmentioning

confidence: 96%

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An efficient tool for the assisted design of SAR ADCs capacitive DACs

et al. 2016

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a b s t r a c tThe optimal design of SAR ADCs requires the accurate estimate of nonlinearity and parasitic capacitance effects in the feedback charge redistribution DAC. Since both contributions depend on the specific array topology, complex calculations, custom modeling and heavy simulations in common circuit design environments are often required. This paper presents a MATLAB-based numerical environment to assist the design of the charge redistribution DACs adopted in SAR ADCs. The tool performs both parametric and statistical simulations taking into account capacitive mismatch and parasitic capacitances computing both differential and integral nonlinearity (DNL, INL). An excellent agreement is obtained with the results of circuit simulators (e.g. Cadence Spectre) featuring up to 10 4 shorter simulation time, allowing statistical simulations that would be otherwise impracticable. The switching energy and SNDR degradation due to static nonlinear effects are also estimated. Simulations and measurements on three designed and two fabricated prototypes confirm that the proposed tool can be used as a valid instrument to assist the design of a charge redistribution SAR ADC and to predict its static and dynamic metrics.

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Section: Cbw Modelmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 96%

An efficient tool for the assisted design of SAR ADCs capacitive DACs

et al. 2016

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“…The threshold levels of the 3-level quantizer are determined in order to further reduce the swing at the output node of the integrator (V out ). For this, the threshold levels have to be set to ± V ref 2 . This way, the output swing is reduced to ±…”

Section: A Principlementioning

confidence: 99%

“…In this case, also the chiparea is very important. Recently, successive approximation register (SAR) converters have been convincingly shown to be the most efficient Nyquist-Rate converters in the 8-10 bit range [1], [2]. However achieving more than 10-bit matching requires an unacceptable silicon area.…”

Section: Introductionmentioning

confidence: 99%

A very compact 1MS/s Nyquist-rate A/D-converter with 12 effective bits

Rombouts

Woestyn

Bock

et al. 2012

2012 Proceedings of the ESSCIRC (ESSCIRC)

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Abstract-We present a very compact analog-to-digital convertor (ADC) for use as a standard cell. To achieve an inherent accuracy of at least 12-bits without trimming or calibration, extended counting A/D-conversion is used. Here, the circuit performs a conversion by passing through two modes of operation: first it works as a 1st-order incremental convertor and then it is reconfigured to operate as a conventional algorithmic converter. This way, we obtain a Nyquist-rate converter that requires only 1 operational amplifier and achieves 12-bit accuracy performance in 13 clock cycles with 9 bit capacitor matching. The circuit is designed in 0.18 µm CMOS with a thick oxide option. The resulting analog core occupies a chip area of only 0.011 mm 2 and the complete digital control and reconstruction logic (including additional test features and storage registers) is 0.02 mm 2 . The analog blocks of the circuit consume 1.2mW and the digital 0.4mW. At a sample rate of 1 MS/s, the peak SNDR is 74.5dB and the dynamic range is 78dB, constant over the Nyquist band. The worst-case integral non-lineairity (INL) is within ±0.55 LSB.

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“…There have been many related works to enhance the performance of the SAR ADCS. These works mainly focus on charge recycling [2], timing control [3] and comparator structure [4]. This work proposes a multiple-phase clock generation based on ring-oscillator structure with dynamic logic to optimize both the speed and power.…”

Section: Introductionmentioning

confidence: 99%

Asynchronous 10MS/s 10-Bit SAR ADC for Wireless Network

Zhang¹,

Guo²,

Yan³

et al. 2014

IJCTE

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Abstract-This paper presents a low power asynchronous 10-bit Successive Approximation Register (SAR) ADC implemented in 0.18μm CMOS process. The ADC is realized fully differentially with a split capacitor array to lower power cost and improve the speed. To further enhance power efficiency and high speed for a relatively moderate resolution, a new asynchronous dynamic logic is utilized to lower the digital power. The multiple-phase clock is generated by a ring-oscillator structure which avoids the high external clock. Offset of the dynamic clocked-comparator is also calibrated through adjusting the threshold voltage. The ADC consumes 500uw at Vdd=1.8v and 10M/s sampling rate.Index Terms-SAR analog to digital converter (ADC), low power, fully dynamic comparator, CMOS, offset cancellation, asynchronous logic.

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A 26 $\mu$W 8 bit 10 MS/s Asynchronous SAR ADC for Low Energy Radios

Cited by 301 publications

References 7 publications

An efficient tool for the assisted design of SAR ADCs capacitive DACs

An efficient tool for the assisted design of SAR ADCs capacitive DACs

A very compact 1MS/s Nyquist-rate A/D-converter with 12 effective bits

Asynchronous 10MS/s 10-Bit SAR ADC for Wireless Network

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