A 28-nm 75-fs_rms Analog Fractional-$N$ Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction

Oscillator Flicker Phase Noise: A Tutorial

“…The V DS becomes symmetric (with a flat bottom, see Fig. 5(b) 4 ) when I H2 sees a resistive characteristic of the CM tank (i.e. ω cm,tank = 2ω 0 ).…”

A 3.2-to-3.8 GHz Harmonic-Mixer-Based Dual-Feedback Fractional-N PLL Achieving -65 dBc In-Band Fractional Spur

“…This means that the proposed PLL can achieve phase noise contribution from the ∆Σ modulator that is N.α−1 times lower than that in the conventional fractional-N PLL. Equation (3) shows that the noise generated in the CP is not amplified either. Since the noise source i n,CP contains nonlinearity-induced fractional spurs and reference spurs due to the non-ideal operation of both the PFD and the CP, the proposed PLL can achieve N.α − 1 times lower spurs than the conventional fractional-N PLL.…”

“…Many different approaches have been proposed to tackle these issues. Works such as [2]- [4] attempt to cancel the deterministic noise from the ∆Σ modulator by using a current DAC [2] or by using a digital-to-time converter [3], [4]. This approach requires gain matching as well as high linearity for the circuit components, which leads to complex calibration schemes such as a least mean square (LMS) algorithm.…”

Jitter-Power Trade-Offs in PLLs

“…Third, as analog-to-digital converters (ADCs) target higher speeds and resolutions, their sampling clock jitter must commensurately fall. State-of-theart PLL design has achieved jitter values in the range of 50 to 75 fs rms at frequencies from 5.5 GHz to 16 GHz [1]- [6].…”