A 29 ns 64 Mb DRAM with hierarchical array architecture

Nakamura, M.; Takahashi, Tsuyoshi; Akiba, T.; Kitsukawa, G.; Morino, Mario; Sekiguchi, T.; Asano, Ichiro; Komatsuzaki, K.; Tadaki, Y.; Songsu, C.; Kajigaya, K.; Tachibana, T.; Satoh, K.

doi:10.1109/isscc.1995.535541

Cited by 9 publications

(4 citation statements)

References 3 publications

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“…The multiplexer, located between LIO and GIO lines, has separate paths for write and read data. The write data driven by the write driver onto the GIO lines is transferred by simple nMOS switches MN5 and MN6 to the corresponding LIO lines while the read data on the LIO line is amplified and transferred to the GIO lines by the LSA [7]. By careful layout, the LSA can be drawn in the bitline sense amplifier (BLSA) area without area penalty.…”

Section: A Hierarchical I/o Lines With Local Sense Amplifiermentioning

confidence: 99%

“…In conventional local sensing where the transistors MN1 and MN2 do not exist [7], a dc current path is formed between the GIO and GIOB lines through the transistors MN3 and MN4 during the write operation because the nonselected LIO lines are precharged to either or , turning the transistors MN3 and MN4 on. The LSA of this work shuts the dc current path off using the transistors MN1 and MN2.…”

Section: A Hierarchical I/o Lines With Local Sense Amplifiermentioning

confidence: 99%

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A 1.8-V 700-mb/s/pin 512-mb DDR-II SDRAM with on-die termination and off-chip driver calibration

Yoo

Kyung

Han

et al. 2004

IEEE J. Solid-State Circuits

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A 512-Mb DDR-II SDRAM has achieved 700-Mb/s/pin operation at 1.8-V supply voltage with 0.12-m DRAM process. The low supply voltage presents challenges in high data rate and signal integrity. Circuit techniques such as hierarchical I/O lines, local sense amplifier, and fully shielded data lines without area penalty have provided improved data access time and, thus, high data rate can be achieved. Off-chip driver with calibrated strength and on-die termination are utilized to give sufficient signal integrity for over 533-Mb/s/pin operation. Index Terms-CMOS, DDR-II, double data rate (DDR), DRAM, hierarchical I/O line, local sense amplifier, low voltage, off-chip driver, on-die termination, SDRAM.

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Section: A Hierarchical I/o Lines With Local Sense Amplifiermentioning

confidence: 99%

Section: A Hierarchical I/o Lines With Local Sense Amplifiermentioning

confidence: 99%

A 1.8-V 700-mb/s/pin 512-mb DDR-II SDRAM with on-die termination and off-chip driver calibration

Yoo

Kyung

Han

et al. 2004

IEEE J. Solid-State Circuits

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show abstract

“…Since the optimal cache line size varies according to the characteristics of incoming graphics applications [12], changing the cache line size to its optimal value results in a lower miss rate. It also reduces power consumption by removing unnecessary sub-wordline activation [17].…”

Section: Reconfigurable Cache Line Sizementioning

confidence: 99%

A reconfigurable multilevel parallel texture cache memory with 75-GB/s parallel cache replacement bandwidth

Park

Kim

Woo

et al. 2002

IEEE J. Solid-State Circuits

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Recently, the level of realism in PC graphics applications has been approaching that of high-end graphics workstations, necessitating a more sophisticated texture data cache memory to overcome the finite bandwidth of the AGP or PCI bus. This paper proposes a multilevel parallel texture cache memory to reduce the required data bandwidth on the AGP or PCI bus and to accelerate the operations of parallel graphics pipelines in PC graphics cards. The proposed cache memory is fabricated by 0.16-m DRAM-based SOC technology. It is composed of four components: an 8-MB DRAM L2 cache, 8-way parallel SRAM L1 caches, pipelined texture data filters, and a serial-to-parallel loader. For high-speed parallel L1 cache data replacement, the internal bus bandwidth has been maximized up to 75 GB/s with a newly proposed hidden double data transfer scheme. In addition, the cache memory has a reconfigurable architecture in its line size for optimal caching performance in various graphics applications from three-dimensional (3-D) games to high-quality 3-D movies. This architecture also leads to optimal power consumption with an adaptive sub-wordline activation scheme. The pipelined texture data filters and the dedicated structure of the L1 caches implemented by the DRAM peripheral transistors show the potential of DRAM-based SOC design with better performance-to-cost ratio. Index Terms-3-D graphics, DRAM-based SOC, DRAM L2 cache, multilevel parallel cache, texture cache. I. INTRODUCTION A S THREE-DIMENSIONAL (3-D) graphics become one of the most important components of multimedia applications today, 3-D graphics processing power has become a major performance index of multimedia systems, such as PCs or portable information terminals [1]-[5]. At present, the level of realism of PC graphics scenes is comparable to that of high-end graphics workstations a few years ago [6], [7]. For the generation of realistic scenes, texture mapping has been frequently used in 3-D graphics [8]. This technique enhances the realism of 3-D graphics scenes by wrapping 3-D model surfaces with two-dimensional (2-D) texture images obtained by scanning the surface of the 3-D objects in real space. By the texture mapping operation, surface details such as color and roughness can easily

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“…For the Samsung DRAM as shown in Figure 8, the slope is nearly constant, which implies that oxide traps dominate the threshold voltage response. The Mitsubishi device has a similar slope and corresponds to about 20 % hole trapping for oxide thickness of 10 nm, which is the approximate thickness of 64 Mb DRAM technologies [4]. However, the magnitude ofthe change is greater than for the Samsung device.…”

Section: Burned-in Devices Inmentioning

confidence: 88%