A 3.2-GHz second-order delta-sigma modulator implemented in InP HBT technology

Jensen, J.F.; Raghavan, G.; Cosand, A.E.; Walden, R.H.

doi:10.1109/4.466070

Cited by 112 publications

(38 citation statements)

References 13 publications

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“…Recently, near ideal performance was reported with an InP HBT second-order modulator with a sampling rate of 3.2 Gs/s and an over-sampling ratio of 32 for a Nyquist rate of 100 Ms/s [19]. This converter technology has GHz and GHz.…”

Section: High-performance Adc Architecturesmentioning

confidence: 99%

Analog-to-digital converter survey and analysis

Walden

1999

IEEE J. Select. Areas Commun.

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1,835

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Abstract-Analog-to-digital converters (ADC's) are ubiquitous, critical components of software radio and other signal processing systems. This paper surveys the state-of-the-art of ADC's, including experimental converters and commercially available parts. The distribution of resolution versus sampling rate provides insight into ADC performance limitations. At sampling rates below 2 million samples per second (Ms/s), resolution appears to be limited by thermal noise. At sampling rates ranging from 2 Ms/s to 4 giga samples per second (Gs/s), resolution falls off by 1 bit for every doubling of the sampling rate. This behavior may be attributed to uncertainty in the sampling instant due to aperture jitter. For ADC's operating at multi-Gs/s rates, the speed of the device technology is also a limiting factor due to comparator ambiguity. Many ADC architectures and integrated circuit technologies have been proposed and implemented to push back these limits. The recent trend toward single-chip ADC's brings lower power dissipation. However, technological progress as measured by the product of the ADC resolution (bits) times the sampling rate is slow. Average improvement is only 1.5 bits for any given sampling frequency over the last six-eight years.Index Terms-Analog-to-digital converters, aperture jitter, comparator ambiguity, input-referred noise, signal-to-noise ratio, spurious-free dynamic range.

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Section: High-performance Adc Architecturesmentioning

confidence: 99%

Analog-to-digital converter survey and analysis

Walden

1999

IEEE J. Select. Areas Commun.

Self Cite

1,835

959

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“…A fully differential DAC eliminates feedback errors associated with unequal DAC rise and fall times [5]. However, the DAC is still vulnerable to quantizer metastability errors.…”

Section: Circuit Designmentioning

confidence: 99%

“…Usually, designers overcome this limitation by employing bootstrapped [5] or negative-resistance loads. These techniques introduce higher order poles, resulting in excess phase delay and thus limiting the oversampling ratio.…”

Section: Circuit Designmentioning

confidence: 99%

“…In bipolar processes, fast, low-offset switches are difficult to implement, and the continuous-time architecture [4] is more readily implemented than the discrete-time, switched-capacitor architecture prevalent in CMOS -ADCs. Continuous-time -modulators have been reported with clock rates as high as 3.2 GHz [5] and 5 GHz [6]. Raghavan et al [7] recently reported a fourth-order bandpass delta-sigma modulator operating at a clock rate of 4 GHz.…”

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confidence: 99%

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An 18-GHz continuous-time Σ-Δ analog-digital converter implemented in InP-transferred substrate HBT technology

Jaganathan

Krishnan

Mensa

et al. 2001

IEEE J. Solid-State Circuits

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“…A first-order topology offers a 9dB SNR improvement for each doubling of the sampling frequency. Second and higher order modulators give better performance [4,5] but they are more complex to design and require sharp filtering in the decimation stage. A first-order implementation was undertaken to prove the concept and establish the fundamental design considerations.…”

Section: Circuit Designmentioning

confidence: 99%