Analog-to-digital converter survey and analysis

Abstract

Abstract-Analog-to-digital converters (ADC's) are ubiquitous, critical components of software radio and other signal processing systems. This paper surveys the state-of-the-art of ADC's, including experimental converters and commercially available parts. The distribution of resolution versus sampling rate provides insight into ADC performance limitations. At sampling rates below 2 million samples per second (Ms/s), resolution appears to be limited by thermal noise. At sampling rates ranging from 2 Ms/s to 4 giga samples per second (Gs/s), resolution falls off by 1 bit for every doubling of the sampling rate. This behavior may be attributed to uncertainty in the sampling instant due to aperture jitter. For ADC's operating at multi-Gs/s rates, the speed of the device technology is also a limiting factor due to comparator ambiguity. Many ADC architectures and integrated circuit technologies have been proposed and implemented to push back these limits. The recent trend toward single-chip ADC's brings lower power dissipation. However, technological progress as measured by the product of the ADC resolution (bits) times the sampling rate is slow. Average improvement is only 1.5 bits for any given sampling frequency over the last six-eight years.Index Terms-Analog-to-digital converters, aperture jitter, comparator ambiguity, input-referred noise, signal-to-noise ratio, spurious-free dynamic range.

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“…While digital electronics has recently enjoyed explosive growth in terms of speed and storage capacity, the performance of analog-to-digital converters (ADCs) has not experienced such improvement [106,107]. The interface between the analog and digital domains has become the major bottleneck in the further advancement of mixed-signal communication, computation, and sensing systems.…”

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“…13, predicted a lower distortion for ) is frequently used [13]. This FOM turns out to be identical for both modes.…”

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“…A recent study on the possibility of a "software-defined" multi-mode GPRS/WCDMA/802.11A transceiver demonstrated that a 14-bit 150 Msps ADC, with a power consumption of less than 50 mW is required for this application [6]. This level of performance is not achievable today with low-cost ADC technology, but given the fact that the power consumption per Msample/sec halves roughly every two years, this level of performance will be achievable in the not-too-distant future [7]. This gap between the performance of ADCs and the requirements of the software-defined radio has historically limited the application of this approach.…”