A 3.3 V 72.2 Mbit/s 802.11n WLAN transformer-based power amplifier in 65 nm CMOS

Abstract

This paper describes the design of a power amplifier (PA) for 802.11n WLAN fabricated in 65 nm CMOS technology. The PA utilizes 3.3 V thick gate oxide (5.2 nm) transistors and a two-stage differential configuration with integrated transformers for input and interstage matching. A methodology used to extract the layout parasitics from electromagnetic (EM) simulations is described. For a 72.2 Mbit/s, 64-QAM, 802.11n OFDM signal at an average and peak output power of 11.6 and 19.6 dBm, respectively, the measured EVM is 3.8%. The PA meets the spectral mask up to an average output power of 17 dBm.

Reliability study of a low-voltage Class-E power amplifier in 130nm CMOS

“…The average drain capacitance of the device was estimated in the off-state [10], while V DS was swept from 0V to 3V, and was equal to 0.7pF/1000µm transistor width. To reduce the resistive losses at the drains and sources, several metal layers were stacked on top of each other as described in [11], but this also adds parasitic capacitance between gate, drain, and source. The parasitic layout capacitances C gd,par and C ds,par ( Fig.…”

“…Simulations of the PA indicated that the peak drain voltage reached levels of 2.5xVDD (3.5V) for a supply voltage of 1.4V as seen in Fig. 7, where the simulation model includes layout parasitics extracted in EM simulations [11], bond wires, PCB tracks, and S-parameters of the lumped matching components. The simulated waveforms can be expected in case the PA is matched identical to the simulated load impedance.…”