A 3-D Device-Level Investigation of a Lag-Free PPD Pixel With a Capacitive Deep Trench Isolation as Shared Vertical Transfer Gate

Alaibakhsh, Hamzeh; Karami, Mohammad Azim

doi:10.1109/ted.2018.2863682

Cited by 5 publications

(2 citation statements)

References 15 publications

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“…It should be noted that the efficiency of the 3D simulation setup is already demonstrated in [17] for our previous pixel to be called 'conventional VTG pixel' in the present work. Fig.…”

Section: Pixel Descriptionsupporting

confidence: 52%

“…Channel separation is achieved by the introduction of an extra implantation layer that pushes the location of the highest potential away from the SiO 2 /Si interface, thus reducing the probability of trapping conduction carriers by interface defects and modifying CTE. This paper proposes a modified structure of our previous work [17], a back‐side‐illuminated (BSI) four transistor (4T) shared vertical TG (VTG) CMOS image sensor (CIS) pixel. This pixel extends the use of CDTI as shared VTG that facilitates pixel miniaturisation and can result in more circuit integration at the pixel surface but suffers from CTI caused by interface trap in the VTG part.…”

Section: Introductionmentioning

confidence: 99%

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3D device‐level simulation of charge separation from sidewall in vertical transfer gate pinned photodiode pixels for noise mitigation

Heidari

Alaibakhsh

Karami

2020

IET Circuits, Devices & Systems

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This study proposes vertical sidewall implantation for noise reduction of CMOS image sensor pixel employing a vertical transfer gate (VTG). The pixel performance is evaluated by 3D device-level simulation. It is concluded that the proposed pixel's output is less sensitive to interface traps compared to similar previous work. In previous backside illuminated shared VTG pixel, which lacks the sidewall implantation for noise mitigation, photogenerated carriers were transferred to the floating diffusion (FD) region along with the interface. In the proposed pixel, the channel is separated from the interface, and photogenerated carriers are transferred with 10 nm distance from VTG. The proposed pixel has a complete charge transfer from the buried pinned photodiode to FD with 1274 e − /µm 2 equilibrium full-well capacity. The conversion gain is 200 μV/e − and the signal-to-noise ratio is 37 dB.

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“…It should be noted that the efficiency of the 3D simulation setup is already demonstrated in [17] for our previous pixel to be called 'conventional VTG pixel' in the present work. Fig.…”

Section: Pixel Descriptionsupporting

confidence: 52%

Section: Introductionmentioning

confidence: 99%