A 30fJ/comparison dynamic bias comparator

Bindra, Harijot Singh; Lokin, Christiaan E.; Annema, Anne-Johan; Nauta, Bram

doi:10.1109/esscirc.2017.8094528

Cited by 38 publications

(23 citation statements)

References 10 publications

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“…A servo-loop has been used, which senses the comparator output and feeds back to the input the opposite offset value until the comparator goes into a metastable state. For the designed V CM of 0.5 V, the 1-σ raw value for both [10,11,25,26] was larger than 11 mV, while it was 9.8 mV for the proposed design ( Figure 6a). After enabling the proposed calibration, the offset was improved to 0.69 mV, set by the designed C INT /C CAL ratio and noise, without compromising the rest of the specifications.…”

Section: (Mv)mentioning

confidence: 96%

“…The implemented self-calibrating comparator performance in terms of delay and noise has been characterized with extracted simulations and compared to the comparators from [10,11,25,26], scaled to 28 nm ( Figure 5). For the comparator delay, the Overdrive Recovery Test (ORT) [27,28] has been used, while the noise has been characterized with both pss + pnoise and transient simulations.…”

Section: Comparator Corementioning

confidence: 99%

“…For the comparator delay, the Overdrive Recovery Test (ORT) [27,28] has been used, while the noise has been characterized with both pss + pnoise and transient simulations. The operating conditions were V DD = 1.0 V and V CM = 0.5 V. The proposed design achieved more than 20% faster regeneration time for small inputs due to the increased gain in the signal path and showed a lower input dependency for a wide range of voltages compared to [10,11,25,26] (Figure 5a). To achieve similar regeneration times, the tail, as well as the latching transistors of the works in [10,11,25,26] had to be upscaled, whose combined contribution increased the total input-referred noise by more than 15% with respect to this design, as shown in Figure 5b.…”

Section: Comparator Corementioning

confidence: 99%

“…Comparator [10,25] Comparator [11,26] This comparator = 0.9 mV = 1.01 mV = 0.78 mV (b) Figure 5. Simulated delay versus ΔV IN for the same offset/noise (a) and cumulative noise distribution for similar delay (b) for [10,11,25,26] and the proposed design.…”

Section: (Mv)mentioning

confidence: 99%

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An 11 GHz Dual-Sided Self-Calibrating Dynamic Comparator in 28 nm CMOS

et al. 2018

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This paper demonstrates a high-speed, low-noise dynamic comparator, employing self-calibration. The proposed dual-sided, fully-dynamic offset calibration is able to reduce the input-referred offset voltage by a factor of ten compared to the uncalibrated value without any speed or noise penalty and with less than 5% power overhead. Moreover, the implemented multi-stage topology significantly advances the state-of-the-art comparator performance, achieving the highest reported operating frequency, as well as the lowest delay slope and sensitivity to supply and common mode variations compared to existing works, with similar energy/comparison. This makes the proposed self-calibrating comparator an ideal candidate for high resolution (>10 b) multi-GHz Analog-to-Digital Converters (ADCs). The 28 nm bulk CMOS prototype measures an input-referred noise and calibrated offset of 0.82 mV and 0.99 mV, respectively clocked at 11 GHz, consuming only 0.89 mW from a 1 V supply, for an area of 0.00054 mm 2 , including calibration.

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Section: (Mv)mentioning

confidence: 96%

Section: Comparator Corementioning

confidence: 99%

Section: Comparator Corementioning

confidence: 99%

Section: (Mv)mentioning

confidence: 99%

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An 11 GHz Dual-Sided Self-Calibrating Dynamic Comparator in 28 nm CMOS

et al. 2018

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“…Based on the circuit of Fig. 2(a), we show that the energy consumption for a given SNR can be reduced through a dynamic bias technique that discharges the output nodes of the pre-amplifier only partially [7]. In this paper we present a detailed analysis of the latch-type comparator with a dynamic bias pre-amplifier ( Fig.…”

Section: Introductionmentioning

confidence: 99%

A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise

Bindra

Lokin

Schinkel

et al. 2018

IEEE J. Solid-State Circuits

Self Cite

149

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A latch-type comparator with a dynamic bias preamplifier is implemented in a 65nm CMOS process. The dynamic bias with a tail capacitor is simple to implement and ensures that the pre-amplifier output nodes are only partially discharged to reduce the energy consumption. The comparator is analyzed and compared to its prior-art in terms of energy consumption and input referred noise voltage. First-order equations are presented that show how to optimize the pre-amplifier for low noise and high gain. Both the dynamic bias comparator and the prior-art are implemented on the same die and measurements show that the dynamic bias can reduce the average energy consumption by about a factor 2.5 for the same input-equivalent noise at an input common mode level of half the supply voltage.

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A low‐power 10‐bit CCP‐based pipelined ADC using a multi‐level variable current source MDAC and an ultra‐low‐power double‐tail dynamic latch

Firouzkouhi

Ashraf

2021

Circuit Theory & Apps

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Summary In this paper, a low‐power 10‐bit 15‐MS/s opamp‐less pipelined analog‐to‐digital converter (ADC) has been proposed. The circuit is comprised of eight 1.5‐bit/stage MDACs and a 2‐bit backend flash ADC. Each 1.5‐bit/stage structure comprises a CCP‐based MDAC which uses a modified multilevel variable‐current‐source (ML‐VCS) scheme. The modified ML‐VCS CCP structure facilitates its usage in a pipeline ADC structure. Also, the proposed ML‐VCS structure improves the speed behavior as well as the power consumption of a 1.5‐bit/stage CCP‐based MDAC structure. In order to further reduce power consumption, an ultra‐low‐power low‐delay double‐tail dynamic latch has been offered which features high‐speed operation. The suggested ADC is simulated using 180‐nm scaled CMOS technology with a 2‐Vp‐p differential full‐scale input voltage. Hspice simulation results show that the ADC exhibits an SNDR of 60‐dB, an ENOB of 9.67 bits, and the FOM of 0.546 PJ/Conv.step at a Nyquist‐rate input frequency. According to the results, the proposed 10‐bit ADC consumes only 6.7‐mW under a 1.8‐V supply voltage.

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A 30fJ/comparison dynamic bias comparator

Cited by 38 publications

References 10 publications

An 11 GHz Dual-Sided Self-Calibrating Dynamic Comparator in 28 nm CMOS

An 11 GHz Dual-Sided Self-Calibrating Dynamic Comparator in 28 nm CMOS

A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise

A low‐power 10‐bit CCP‐based pipelined ADC using a multi‐level variable current source MDAC and an ultra‐low‐power double‐tail dynamic latch

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