A 32 Gb/s Data-Interpolator Receiver With Two-Tap DFE Fabricated With 28-nm CMOS Process

Doi, Yoshihiro; Shibasaki, Takayuki; Danjo, Takumi; Chaivipas, Win; Hashida, Takusi; Miyaoka, Hiroki; Hoshino, Masanori; Koyanagi, Yoichi; Yamamoto, Takuji; Tsukamoto, Sanroku; Tamura, Hirotaka

doi:10.1109/jssc.2013.2278805

Cited by 12 publications

(2 citation statements)

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“…Additionally, the FFE and XTC are merged together with the SST driver in this work to compensate for both the ISI and FEXT. Table IV is the RX performance summary and comparison with other similar designs [14]- [16], [20], [22], which indicates that the RX implemented in this paper can compensate for the most serious channel loss. The eye opening and the DFE power efficiency TABLE III TX PERFORMANCE SUMMARY AND COMPARISON TABLE IV RX PERFORMANCE SUMMARY AND COMPARISON are also comparable to the others.…”

Section: Performance Comparisonmentioning

confidence: 90%

A 70 mW 25 Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset With 40 dB of Equalization in 65 nm CMOS Technology

Yuan

Wang

et al. 2016

IEEE Trans. Circuits Syst. I

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A 25 Gb/s transmitter (TX) and receiver (RX) chipset designed in a 65 nm CMOS technology is presented. The proposed quarter-rate TX architecture with divider-less clock generation can not only guarantee the timing constraint for the highest-speed serialization, but also save power compared with the conventional designs. A source-series terminated (SST) driver with a 2-tap feedforward equalizer (FFE) and a far-end crosstalk canceller (XTC) is implemented in the TX chip. The RX chip employs an adaptive quarter-rate 2-tap decision-feedback equalizer (DFE) and a baud-rate clock and data recovery (CDR). The power-efficient DFE uses the combination of the soft-decision technique and a new dynamic structure. The DFE adaption logic and baud-rate CDR logic share a set of error samplers to save power and area. A hybrid alternate clock scheme is proposed to satisfy the timing requirement and reduce the power consumption further. The measurement results show that the TX and RX chipset totally compensates for a Nyquist channel loss of more than 40 dB, and consumes only 70 mW from a 1.2 V supply when operating at 25 Gb/s.

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Section: Performance Comparisonmentioning

confidence: 90%

A 70 mW 25 Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset With 40 dB of Equalization in 65 nm CMOS Technology

Yuan

Wang

et al. 2016

IEEE Trans. Circuits Syst. I

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“…To reduce the power consumption of the DFE, [17] performs interpolation in the analog domain prior to the ADC. However, performing analog data interpolation (DI) increases the complexity of the design.…”

Section: A Interpolation-first Schemementioning

confidence: 99%

A 3x blind ADC-based CDR for a 20 dB loss channel

Jalali

Chen

Liang

et al. 2015

IEEE Trans. Circuits Syst. I

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This paper proposes using a 3-bit ADC to blindly sample the received data from a channel with 20 dB loss at Nyquist at 3 the baud rate. By moving from 2 to 3 sampling, we reduce the required ADC resolution from 5-bit to 3-bit, thereby reducing the overall power consumption by a factor of 2. Measurements from our test chip fabricated in Fujitsu's 65 nm CMOS show a high frequency jitter tolerance of 0.25 UIpp for a 5 Gb/s PRBS31 with a 60 FR4 channel. Index Terms-ADC-based CDR, blind-sampling CDR, clock and data recovery, feed-forward CDR.1549-8328

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