2014
DOI: 10.1109/jssc.2014.2353798
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A 32 nm Embedded, Fully-Digital, Phase-Locked Low Dropout Regulator for Fine Grained Power Management in Digital Circuits

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Cited by 67 publications
(13 citation statements)
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“…To ensure and stale the power supplying unit, the human machine interface between human and power grid is initialized [17]. The IEEE802.11 (WLAN) [18], IEEE 802.15 (WPAN) [19], and IEEE802.15.4 (LR-WPAN) [11]. In the design, the home gateway known as VEN which is exposed to the human power factor utilization and how much power consumption they have used and how amount of power cost is deduced in daily basis.…”
Section: A Iot Based Energy Management Systemmentioning
confidence: 99%
“…To ensure and stale the power supplying unit, the human machine interface between human and power grid is initialized [17]. The IEEE802.11 (WLAN) [18], IEEE 802.15 (WPAN) [19], and IEEE802.15.4 (LR-WPAN) [11]. In the design, the home gateway known as VEN which is exposed to the human power factor utilization and how much power consumption they have used and how amount of power cost is deduced in daily basis.…”
Section: A Iot Based Energy Management Systemmentioning
confidence: 99%
“…where t rise (V RIPPLE MAX ) can be estimated using (13). Since the upper bound of the ripple magnitude is used in the above estimation, the obtained result should be the lower bound of the ripple frequency, noting that the larger the ripple magnitude is, the larger t rise is.…”
Section: Modelling Ldo Output Steady-state Ripplementioning
confidence: 99%
“…Finally, the positive root of (36) corresponds to the rise time of the LDO output to ±ΔV ref . Its solution is given explicitly in (13).…”
Section: Appendixmentioning
confidence: 99%
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“…Literature [13] proposed a DLDO based TSPC which has achieved a faster loop time with the penalty of degrading of current efficiency. Literature [14] proposed a DLDO controlled by phase-locked clock, which achieves a fast transient response, but the stacking of power PMOS causes a drop of current efficiency and make it unable to work at very low voltages. A DLDO combined coarse-tuning and fine-tuning (CFT) proposed by [15] makes a good tradeoff between power consumption and transient response time, but it needs two clock, which make a large area overhead.…”
Section: Introductionmentioning
confidence: 99%