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An increasing number of power domains and of power states per domain, as well as decreasing decoupling capacitance per local grid and ultra-wide current dynamic range of digital load circuits (for low power on one end while maintaining performance at another) necessitate the design of high-efficiency, compact on-die voltage regulators providing ultra-fine grained spatio-temporal voltage distribution [1,2]. Digitally implementable linear regulators operated in low-dropout (LDO) mode, based on continuous time or discrete time control, exhibit process and voltage scalability [3][4][5], thus supplementing their analog counterparts [6].This paper presents a discrete-time, fully digital, scan-programmable LDO macro in 0.13μm technology featuring greater than 90% current efficiency across a 50× current range, and 8× improvement in transient response time in response to large load steps. The baseline design (Fig. 5.6.1) features a 128b barrel shifter that digitally controls 128 identical power PMOS devices to provide load and line regulation at the node V REG , for a scan-programmable fine-grained synthetic load. A clocked comparator, which eliminates the need for any bias current, controls the direction of shift, D. The programmable mux-select signals, MUX1 and MUX2, provide controllable closed loop gains, K BARREL , of 1 to 3×. Since at any clock edge only 1, 2 or 3 shifts can occur (depending on the gain setting), fine-grained clock gating is enabled by dividing the 128b shifter into four sections and only enabling the clock to the section(s) where the shift occurs ( Fig. 5.6.1).

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In recent years, several designs that use in-memory processing to accelerate machinelearning inference problems have been proposed. Such designs are also a perfect fit for discrete, dynamic, and distributed systems that can solve large-dimensional optimization problems using iterative algorithms. For in-memory computations, ferroelectric field-effect transistors (FerroFETs) owing to their compact area and distinguishable multiple states offer promising possibilities. We present a distributed architecture that uses FerroFET memory and implements in-memory processing to solve a template problem of least squares minimization. Through this architecture, we demonstrate an improvement of 21× in energy efficiency and 3× in compute time compared to a static random access memory (SRAM)-based processing-inmemory (PIM) architecture. INDEX TERMS Distributed computing, emerging, ferroelectric field-effect transistors (FerroFETs), hardware, in-memory processing, least square, optimization, post-CMOS.