All-Digital Low-Dropout Regulator with Adaptive Control and Reduced Dynamic Stability for Digital Load Circuits

Nasir, Saad Bin; Gangopadhyay, Samantak; Raychowdhury, Arijit

doi:10.1109/tpel.2016.2519446

Cited by 80 publications

(21 citation statements)

References 9 publications

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“…Equation (5) provides insights into the stability of the proposed DLDO. Compared with the transfer function of the traditional DLDO in [20], the PI controller produces an extra zero at z = (K P − K I /F S ) /K P . The bandwidth and transient response speed of the proposed system are increased.…”

Section: System Hybrid Modelmentioning

confidence: 99%

A Fast Transient Response Digital LDO with a TDC-Based Signal Converter

Zhang¹,

Wan²,

Geng³

et al. 2020

Electronics

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The digital low drop-out regulator (LDO) has been used widely in digital circuits for its low supply voltage characteristics. However, as the traditional digital LDOs regulate the output voltage code at a rate of 1 bit per clock cycle, the transient response speed is limited. This paper presents a digital LDO to improve transient response speed with a multi-bit conversion technique. The proposed technology uses a voltage sensor and a time-to-digital converter to convert the output voltage to digital codes. Based on a 65-nm CMOS process, the proposed DLDO reduces the settling time from 147.8 ns to 25.2 ns on average and the response speed is improved by about six times.

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Section: System Hybrid Modelmentioning

confidence: 99%

A Fast Transient Response Digital LDO with a TDC-Based Signal Converter

Zhang¹,

Wan²,

Geng³

et al. 2020

Electronics

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show abstract

“…The datasheet states that in order to guarantee VR stability, the ESR value must be between 0.3 to 10 Ω. The corresponding undershoot and overshoot voltages related to this stable ESR range act as the specification during stability determination for another operating points [25], [5]. For example, for load current of 50 mA and ESR of 0.3 Ω, the undershoot and overshoot voltages are US 1 and OS1 1 V, accordingly.…”

Section: Manual Vr Characterizationmentioning

confidence: 99%

“…VR converts the noisy and unstable voltage and current input supply to a stable, constant, accurate, and load-independent output supply [1]. VR has received much attention recently, mainly low dropout voltage type VR, due to the emerging market of new applications such as system-on-chip and Internet-of-Things, which require tight power consumption specification with stable and lower output voltages [2]- [4]. An output capacitor is connected to the VR output terminal to ensure stability.…”

Section: Introductionmentioning

confidence: 99%

Critical Equivalent Series Resistance Estimation for Voltage Regulator Stability Using Hybrid System Identification and Neural Network

Zaman

Mustafa

Hussain

2017

International Journal on Advanced Science, Engineering and Information Technology

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Output capacitor in the voltage regulator (VR) circuit ensures stability especially during fast load transients. However, the capacitor parasitic, namely equivalent series resistance (ESR), may cause unstable VR operation. VR characterization in terms of ESR suggests stable range of capacitor ESR based on the ESR tunnel graph in the VR datasheet. Specifically, the stable ESR range is the critical ESR value, which lies on the failure region boundary of ESR tunnel graph. New or updated ESR tunnel graph through characterization is required for new product development or quality assurance purpose. However, the characterization is typically conducted manually in industry, thereby increases the manufacturing time and cost. Therefore, this work proposed a characterization approach that can reduce the time to determine the ESR tunnel graph based on the hybrid system identification and neural network (SI-NN) approach. This method utilised system identification (SI) to estimate the VR circuit model for certain operating points before predicting the transfer function coefficients for the remaining points using radial basis function neural network (RBFNN). Eventually, the critical ESR of failure region boundary was estimated. This hybrid SI-NN approach able to reduce the number of data that would be acquired manually to 25% compared to manual characterization, while provides critical ESR estimation with error less than 2%.

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“…A Low-Dropout (LDO) regulator is widely utilized as a post-regulator to provide a clean supply voltage for a system-on-chip (SoC) [8]. Traditional analog LDO (ALDO) cannot operate at very low voltages due to the presence of an analog amplifier [9,10]. Digital LDO has been proposed to solve this problem [11].…”

Section: Introductionmentioning

confidence: 99%

A Fast-Transient All-Digital LDO with Adaptive Clock Technique

Jia

Qiao

et al. 2019

Electronics

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To get a better tradeoff between the transient performance and current efficiency of Digital Low-Dropout (DLDO) regulator, this paper proposes an all-digital Low-Dropout (LDO) regulator with adaptive clock technique. The sample clock is supplied by a proposed digital oscillator (DOSC) whose output frequency can be changed seamlessly. The frequency of sample clock and loop gain boost adaptively when the output voltage undershoot/overshoot is detected. Proposed DLDO integrates a ripple controller to eliminate steady-state supply ripple and reduce steady-state power. The proposed DLDO is simulated at Semiconductor Manufacturing International Corporation (SMIC) 55 nm with 5.03e-4 mm2 active area. The simulation results show that the operating voltage of proposed DLDO can be down to 0.5 V and the peak current efficiency is 99.99%. The measured voltage undershoot is 40 mV and transient response time is 500 ns with load step of 10 to 800 uA.

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All-Digital Low-Dropout Regulator with Adaptive Control and Reduced Dynamic Stability for Digital Load Circuits

Cited by 80 publications

References 9 publications

A Fast Transient Response Digital LDO with a TDC-Based Signal Converter

A Fast Transient Response Digital LDO with a TDC-Based Signal Converter

Critical Equivalent Series Resistance Estimation for Voltage Regulator Stability Using Hybrid System Identification and Neural Network

A Fast-Transient All-Digital LDO with Adaptive Clock Technique

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