UVFR: A Unified Voltage and Frequency Regulator with 500MHz/0.84V to 100KHz/0.27V operating range, 99.4% current efficiency and 27% supply guardband reduction

Gangopadhyay, Samantak; Nasir, Saad Bin; Sathe, Visvesh; Raychowdhury, Arijit

doi:10.1109/esscirc.2016.7598307

Cited by 12 publications

(9 citation statements)

References 7 publications

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“…To minimize the guardband, it was proposed recently to combine the V REG and F REG regulation loops into a single unified loop. This loop can be based on an LDO [65], switched capacitor [64], or buck converter [66]- [68]. Buckand LDO-based UVFRs are shown in Fig.…”

Section: B State-of-the-art Uvfrsmentioning

confidence: 99%

“…It reduced the processor's overall energy consumption by 48% while supplying V DD of 1.0V. Due to the reduction of the guardband by using UVFR, the UVFR in [65] reduced the overall supply voltage of the load circuits by 27%. Furthermore, it should also be noted that UVFRs require F REF only.…”

Section: B State-of-the-art Uvfrsmentioning

confidence: 99%

“…There are some FR-DLDOs [65], [69] that can be utilized in the proposed heterogeneous PDN. The FR-DLDO in [69] successfully operates at under-or near-threshold voltage levels with dynamic DVS.…”

Section: Proposed Heterogeneous Pdn Using Frequency-referenced Dldosmentioning

confidence: 99%

“…In addition, its loop response time is also too slow, so it cannot meet the fast switching current demands of SoC load circuits. The UVFR in [65] has an enhanced loop response time and a faster load-transient response time (T R ). But its current driving capability is also minimal at 6 mA.…”

Section: Proposed Heterogeneous Pdn Using Frequency-referenced Dldosmentioning

confidence: 99%

“…But its current driving capability is also minimal at 6 mA. To overcome these limitations of the FR-DLDOs [65], [69], a fast-transient FR-DLDO with a large current-driving capacity and wide regulation range is presented in the next section [63]. The FR-DLDO achieves a faster transient response time due to its transient-boost control.…”

Section: Proposed Heterogeneous Pdn Using Frequency-referenced Dldosmentioning

confidence: 99%

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Power Delivery Networks for Embedded Mobile SoCs: Architectural Advancements and Design Challenges

Akram

Hwang

2021

IEEE Access

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Conventional power delivery networks (PDNs) and power management techniques using off-chip power converters with bulky passive components cannot meet the ever-evolving power delivery requirements of high-performance modern system-on-chips (SoCs). In SoCs, heterogeneous components, including multi-core processors and mixed-signals peripheral circuits, require state-of-the-art PDNs to provide high-quality power-on-demand with minimum latency, simultaneously achieving the small-factor, high conversion efficiency, and minimum current consumption. To satisfy these power delivery requirements, various PDNs have been developed over the past decades, such as the conventional architectures using off-chip power converters, architectures using in-package power converters and fully-integrated power converters, and heterogeneous architectures (off-chip power converters and on-chip regulators). This paper reviews these architectural advancements of the PDNs and their advantages and limitations, which leads us to discuss a heterogeneous PDN structure consisting of a highly efficient off-chip switching-mode power converter and multiple highly precise small linear regulators integrated on chip at point-of-load locations. The heterogeneous PDN has been proved one of the most suitable architectures to achieve high-quality finegrained on-chip power delivery and management in SoCs. This paper also discusses unified voltage and frequency regulators (UVFRs), which support dynamic-variation-aware dynamic voltage and frequency scaling (DVFS) for fine-grained power management in multi-core processors. Based on the UVFR, we propose a modified heterogeneous PDN using frequency-referenced digital low-dropout regulators (FR-DLDOs) for more efficient DVFS, eliminating the need for band-gap circuits to provide reference voltages. As an exemplary implementation of FR-DLDO for this PDN, we present an FR-DLDO with a transientboost control, which accelerates the transient response. The transient-boost control is activated dynamically only when an abrupt change happens out of the steady state. The implemented FR-DLDO fabricated in a 40-nm CMOS process outperforms other FR-DLDOs in the figure-of-merit and peak power efficiency while driving 40 mA of load current. INDEX TERMS Power delivery network (PDN); fine-grained power management; dynamic-voltage and frequency scaling (DVFS); dynamic-voltage scaling (DVS); low-dropout regulator (LDO); digital LDO; unified-voltage and frequency regulator (UVFR); frequency-referenced digital LDO (FR-DLDO); transientboost control.

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Section: B State-of-the-art Uvfrsmentioning

confidence: 99%

Section: B State-of-the-art Uvfrsmentioning

confidence: 99%

Section: Proposed Heterogeneous Pdn Using Frequency-referenced Dldosmentioning

confidence: 99%

Section: Proposed Heterogeneous Pdn Using Frequency-referenced Dldosmentioning

confidence: 99%

Section: Proposed Heterogeneous Pdn Using Frequency-referenced Dldosmentioning

confidence: 99%

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Power Delivery Networks for Embedded Mobile SoCs: Architectural Advancements and Design Challenges

Akram

Hwang

2021

IEEE Access

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show abstract

Conclusion

Reyserhove¹,

Dehaene²

2019

Efficient Design of Variation-Resilient Ultra-Low Energy Digital Processors

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A Self-Clocked TDC-Based Unified Clock and Voltage Regulator with Replica Frequency-Locked Loop and Hysteresis Switching in 65nm CMOS

Wang

Mok

2022

2022 IEEE Asian Solid-State Circuits Conference (A-Sscc)

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UVFR: A Unified Voltage and Frequency Regulator with 500MHz/0.84V to 100KHz/0.27V operating range, 99.4% current efficiency and 27% supply guardband reduction

Cited by 12 publications

References 7 publications

Power Delivery Networks for Embedded Mobile SoCs: Architectural Advancements and Design Challenges

Power Delivery Networks for Embedded Mobile SoCs: Architectural Advancements and Design Challenges

Conclusion

A Self-Clocked TDC-Based Unified Clock and Voltage Regulator with Replica Frequency-Locked Loop and Hysteresis Switching in 65nm CMOS

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