A 32b CMOS microprocessor with on-chip instruction and data caching and memory management

Archer, David W.; Deverell, D.R.; Fox, Frank; Gronowski, P.E.; Jain, Alok; Leary, M.; Olesin, A.; Persels, S.; Rubinfeld, P.I.; Schumacher, Dan; Supnik, Bob; Thrush, T.

doi:10.1109/isscc.1987.1157147

Cited by 7 publications

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An area model for on-chip memories and its application

Mulder

Quach

Flynn

1991

IEEE J. Solid-State Circuits

165

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Absfrud --In the implementation of a processor, it is often necessary to abstract cost constraints into architecture measures for making trade-offs. An important cost measure for an on-chip memory is its occupied silicon area. Since the performance of an on-chip memory is characterized by size (storage capacity), a mapping from size to area is needed. Simple models have been proposed in the past for such a purpose. These models, however, are of unproven validity and only apply when comparing relatively large buffers ( > 128 words for caches, > 32 words for register sets) of the same structure (e.g., cache versus cache).In this paper we present an area model for on-chip memories. The area model considers the supplied bandwidth of a memory cell and includes such buffer overhead as control logic, driver logic, and tag storage, thereby permitting comparison of data buffers of different structures and arbitrary sizes. The model gave less than 10% error when verified against real caches and register files. We then show that comparing cache performance as a function of area, rather than size, leads to a significantly different set of organizational trade-offs.

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