A 32Gb/s 133mW PAM-4 transceiver with DFE based on adaptive clock phase and threshold voltage in 65nm CMOS

Tang, Liangxiao; Gai, Weixin; Shi, Linqi; Xiao, Xiangheng; Sheng, Kai; He, Ai

doi:10.1109/isscc.2018.8310210

Cited by 37 publications

(23 citation statements)

References 5 publications

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“…e nonideal characteristics of transmission channels mainly include skin e ect, dielectric loss, return loss, crosstalk, and all kinds of noises. Among which, the skin e ect and dielectric loss are main reasons for high-frequency channel losses [4,5]. eir impacts can be expressed by…”

Section: Nonideal Factors Of Channelmentioning

confidence: 99%

A 1.25–12.5 Gbps Adaptive CTLE with Asynchronous Statistic Eye-Opening Monitor

Cai

Zhao

Zhou

2018

Journal of Electrical and Computer Engineering

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The equalization of a large attenuation signal and multirate communication in high-speed serial interface is hard to balance. To overcome this difficulty, an adaptive equalization system with optimized eye-opening monitor is proposed. The designed eye-opening monitor is based on the asynchronous statistic eye diagram tracking algorithm, and the eye diagram is obtained by undersampling with the low-speed asynchronous clock. With the eye-opening monitor into the adaptive loop, an adaptive equalization system combined with continuous-time linear equalization (CTLE) is completed. And the inductor peaking technology is used to improve the capacity of compensation. With SMIC 28 nm CMOS process to achieve the overall design, the power consumption and core chip area are 12 mW @ 12.5 Gbps and 0.12 mm2, respectively. And postsimulation results show that it can offer compensation from 6 to 21 dB for 1.25–12.5 Gbps range of receiving data, which achieves a large range of data rate and channel loss, and its power efficiency is 0.046 pJ/bit/dB for the worst case, which is better than most previous works.

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Section: Nonideal Factors Of Channelmentioning

confidence: 99%

A 1.25–12.5 Gbps Adaptive CTLE with Asynchronous Statistic Eye-Opening Monitor

Cai

Zhao

Zhou

2018

Journal of Electrical and Computer Engineering

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“…DFE can effectively eliminate inter-symbol interference caused by finite band, crosstalk, and reflection, but it is effective to eliminate the precursor [6,7,8,9]. Therefore, the combination of CTLE and DFE is widely used to eliminate inter-symbol interference at the receiver [10,11,12,13,14]. Because of temperature variation, material properties, length and bends, it is very important for equalizer to automatically detect and critically compensate for the high frequency loss of channel.…”

Section: Introductionmentioning

confidence: 99%

A 36 Gb/s wireline receiver with adaptive CTLE and 1-tap speculative DFE in 0.13 µm BiCMOS technology

Zhang

Yang

2020

IEICE Electron. Express

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This paper presents a 36 Gb/s receiver equalizer including an adaptive continuous time linear equalizer (CTLE), which is based on slope detection and a half-rate speculative decision feedback equalizer (DFE) in 0.13 µm BiCMOS technology for high speed serial link. The CTLE with middle frequency compensation can not only adjust the ratio of high frequency and low frequency components adaptively, but also provide a small amount of equalization to middle frequency range. A half-rate speculative DFE, which is connected to the back of the CTLE, can satisfy the time constraints and eliminate the residual intersymbol interference. The chip area including pads is about 1.2 mm 2 and the power consumption is about 750 mW under 3.3 V power supply. Measurement results show that the receiver chip can effectively equalize 24 dB loss at Nyquist frequency and a clear eye diagram can be captured at 36 Gb/s.

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“…RS (Reed-Solomn) (544,514) is also deployed to raise the performance of bit error rate (BER) further and compensate the inherent SNR loss of about 9.5 dB compared with NRZ one. However, the error propagation of decision feedback equalizer (DFE) in the receiver, which easily contributes to long burst error beyond the error correction capability of FEC coding, may harm the FEC performance to some extent [4].…”

Section: Introductionmentioning

confidence: 99%

DFE Error Propagation and FEC Interleaving for 400GbE PAM4 Electrical Lane

Zhan

Zhang

2020

IEICE Trans. Electron.

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This paper analyzes the effect of error propagation of decision feedback equalizer (DFE) for PAM4 based 400 Gb/s Ethernet. First, an analytic model for the error propagation is proposed to estimate the probability of different burst error length due to error propagation for PAM4 link system with multi-tap TX FFE (Feed Forward Equalizer) + RX DFE architecture. After calculating the symbol error rate (SER) and bit error rate (BER) based on the probability model, the theoretical analysis about the impact of different equalizer configurations on BER is compared with the simulation results, and then BER performance with FEC (Forward Error Correction) is analyzed to evaluate the effect of DFE error propagation on PAM4 link. Finally, two FEC interleaving schemes, symbol and bit interleaving, are employed in order to reduce BER further and then the theoretical analysis and the simulation result of their performance improvement are also evaluated. Simulation results show that at most 0.52 dB interleaving gain can be achieved compared with non-interleaving scheme just at a little cost in storing memory and latency. And between the two interleaving methods, symbol interleaving performs better compared with the other one from the view of tradeoff between the interleaving gain and the cost and can be applied for 400 Gb/s Ethernet.

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A 32Gb/s 133mW PAM-4 transceiver with DFE based on adaptive clock phase and threshold voltage in 65nm CMOS

Cited by 37 publications

References 5 publications

A 1.25–12.5 Gbps Adaptive CTLE with Asynchronous Statistic Eye-Opening Monitor

A 1.25–12.5 Gbps Adaptive CTLE with Asynchronous Statistic Eye-Opening Monitor

A 36 Gb/s wireline receiver with adaptive CTLE and 1-tap speculative DFE in 0.13 µm BiCMOS technology

DFE Error Propagation and FEC Interleaving for 400GbE PAM4 Electrical Lane

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