A 32nm 3.1 billion transistor 12-wide-issue Itanium<sup>®</sup> processor for mission-critical servers

Riedlinger,; Bhatia, '; Biro,; Bowhill,; Fetzer,; Gronowski,; Grutkowski,

doi:10.1109/isscc.2011.5746230

Cited by 39 publications

(26 citation statements)

References 2 publications

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“…In order to quantify voltage margin levels in a modern microprocessor, experiments were conducted on two Intel Itanium II 9560 8-core processors [24] running on an HP Integrity BL860c-i4 server. More details about the evaluation platform and methodology are presented in Section 5.…”

Section: Motivationmentioning

confidence: 99%

“…For conservative cores the V dd is raised by an increment for each correctable error flagged. Once the Governor determines the appropriate action to take, it writes Table 3: Summary of the ECC protection in the Intel Itanium 9560 processor core [23].…”

Section: Voltage Speculation Governormentioning

confidence: 99%

“…According to the available documentation [23], the Itanium 9560 processor has several functional blocks protected by ECC. These are listed in Table 3.…”

Section: System Architecturementioning

confidence: 99%

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Dynamic reduction of voltage margins by leveraging on-chip ECC in Itanium II processors

BachaAnys

TeodorescuRadu

2013

SIGARCH Comput. Archit. News

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Lowering supply voltage is one of the most effective approaches for improving the energy efficiency of microprocessors. Unfortunately, technology limitations, such as process variability and circuit aging, are forcing microprocessor designers to add larger voltage guardbands to their chips. This makes supply voltage increasingly difficult to scale with technology. This paper presents a new mechanism for dynamically reducing voltage margins while maintaining the chip operating frequency constant. Unlike previous approaches that rely on special hardware to detect and recover from timing violations caused by low-voltage execution, our solution is firmware-based and does not require additional hardware. Instead, it relies on error correction mechanisms already built into modern processors. The system dynamically reduces voltage margins and uses correctable error reports raised by the hardware to identify the lowest, safe operating voltage. The solution adapts to core-to-core variability by tailoring supply voltage to each core's safe operating level. In addition, it exploits variability in workload vulnerability to low voltage execution. The system was prototyped on an HP Integrity Server that uses Intel's Itanium 9560 processors. Evaluation using SPECjbb2005 and SPEC CPU2000 workloads shows core power savings ranging from 18% to 23%, with minimal performance impact.

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Section: Motivationmentioning

confidence: 99%

Section: Voltage Speculation Governormentioning

confidence: 99%

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Dynamic reduction of voltage margins by leveraging on-chip ECC in Itanium II processors

BachaAnys

TeodorescuRadu

2013

SIGARCH Comput. Archit. News

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“…Technology scaling is fueling integration of larger on chip caches in processor design (e.g., up to 50 MB [30]). In order to enable ultra-low power consumption, Angstrom cores need to feature voltage-scalable SRAMs.…”

Section: Intra-core Adaptationmentioning

confidence: 99%

Self-aware computing in the Angstrom processor

Hoffmann¹,

Holt²,

Kurian³

et al. 2012

Proceedings of the 49th Annual Design Automation Conference

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Addressing the challenges of extreme scale computing requires holistic design of new programming models and systems that support those models. This paper discusses the Angstrom processor, which is designed to support a new Self-aware Computing (SEEC) model. In SEEC, applications explicitly state goals, while other systems components provide actions that the SEEC runtime system can use to meet those goals. Angstrom supports this model by exposing sensors and adaptations that traditionally would be managed independently by hardware. This exposure allows SEEC to coordinate hardware actions with actions specified by other parts of the system, and allows the SEEC runtime system to meet application goals while reducing costs (e.g., power consumption).

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“…Moreover, technology scaling is fueling integration of larger on chip caches (50MB reported in [3]). Thus, an energy sensing circuit that is capable of generating a digital representation of absolute energy per operation (EOP) consumed by the caches would provide useful information to the system.…”

Section: Introductionmentioning

confidence: 99%

An embedded energy monitoring circuit for a 128kbit SRAM with body-biased sense-amplifiers

Sinangil

Chandrakasan

2012

2012 IEEE Asian Solid State Circuits Conference (A-Sscc)

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Abstract-Embedded energy monitoring of critical system components can be used to enable better power management by capturing run time system conditions such as temperature and application load. In this work, an energy sensing circuit that provides digitally represented absolute energy per operation of a 128kbit SRAM is presented. Designed in a 65nm low-power CMOS process, SRAMs can operate down to 370 mV. Energy sensing circuit consumes 16.7µ µ µ µW during sensing at 1.2V (only 0.28% of SRAM active power at the same voltage). For improved performance, SRAMs utilize body-biased PMOSinput strong-arm type sense amplifiers that can achieve 45% tighter input offset distribution for only ~3.5% of total SRAM area overhead.

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A 32nm 3.1 billion transistor 12-wide-issue Itanium^® processor for mission-critical servers

Cited by 39 publications

References 2 publications

Dynamic reduction of voltage margins by leveraging on-chip ECC in Itanium II processors

Dynamic reduction of voltage margins by leveraging on-chip ECC in Itanium II processors

Self-aware computing in the Angstrom processor

An embedded energy monitoring circuit for a 128kbit SRAM with body-biased sense-amplifiers

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A 32nm 3.1 billion transistor 12-wide-issue Itanium® processor for mission-critical servers

Cited by 39 publications

References 2 publications

Dynamic reduction of voltage margins by leveraging on-chip ECC in Itanium II processors

Dynamic reduction of voltage margins by leveraging on-chip ECC in Itanium II processors

Self-aware computing in the Angstrom processor

An embedded energy monitoring circuit for a 128kbit SRAM with body-biased sense-amplifiers

Contact Info

Product

Resources

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A 32nm 3.1 billion transistor 12-wide-issue Itanium^® processor for mission-critical servers