An embedded energy monitoring circuit for a 128kbit SRAM with body-biased sense-amplifiers

Sinangil, Yildiz; Chandrakasan, Anantha P.

doi:10.1109/ipec.2012.6522629

Cited by 5 publications

(3 citation statements)

References 8 publications

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“…Nowadays, large embedded memories (primarily SRAM) are used in IoT devices for the storage of instructions and data [1,2]. Consequently, SRAMs are the most common type of on-chip memories and a significant fraction of chip area has been allocated for SRAMs in modern SoCs as highly-parallelized designs often benefit from larger on-chip storage [3]. Hence, careful design of robust SRAM for ultra-low power applications is in high demand.…”

Section: Introductionmentioning

confidence: 99%

A 9 T SRAM cell with data-independent read bitline leakage and improved read sensing margin for low power applications

Sharif¹,

Ahmad²,

Alam³

2022

Semicond. Sci. Technol.

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Read decoupled SRAM cells were proposed to address the conflicting Read and Write requirements in conventional 6T SRAM cells. However, even read decoupled SRAM cells face several challenges like degraded cell stability, data dependent read bitline (RBL) leakage, deteriorated RBL swing which causes the failure in read sensing at scaled voltages. Therefore, in this work, we propose a read decoupled 9T SRAM cell which improves the read performance. The proposed cell utilizes decoupled read port that significantly improves the read delay, ION/IOFF ratio, bitline leakage as compared to the existing read decoupled cells. The proposed read buffer, having only one transistor in the read path, offers much lower read delay as compared to the existing read buffers. The RBL leakage in the proposed design is also data independent, which significantly improves the RBL sensing margin. We analyse and compare the proposed SRAM cell with existing cells using HSPICE simulations with 16nm FinFET PTM technology. We observe that at a voltage of VDD = 0.35V, the proposed SRAM cell offers ~55% smaller read delay with only 8% increase in leakage power as compared to conventional 6T cell. However, the proposed SRAM cell incurs smallest leakage penalty and offers fastest read operation than the existing read buffer based SRAM cells. Attributed to the negligible bitline leakage in the proposed cell, it offers the highest RBL sensing voltage attributed to closeness of RBL voltage for read ‘1’ to VDD as compared with the other cells. Monte Carlo simulations are also carried out to confirm the robustness of the proposed design under PVT variations. We observe that the proposed SRAM cell is robust and supports voltage scaling and hence could be an attractive choice for low voltage and low power applications.

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Section: Introductionmentioning

confidence: 99%

A 9 T SRAM cell with data-independent read bitline leakage and improved read sensing margin for low power applications

Sharif¹,

Ahmad²,

Alam³

2022

Semicond. Sci. Technol.

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“…However, power models cannot fully represent the actual profile of a complex processor system. Absolute energy monitoring circuits are demonstrated in [3], but additional benefits can be obtained by integrating them within the DC/DC converters. Recent work illustrates an energy monitoring circuit embedded into a DC/DC converter [4].…”

Section: Introductionmentioning

confidence: 99%

A self-aware processor SoC using energy monitors integrated into power converters for self-adaptation

Sinangil

Neuman

Sinangil

et al. 2014

2014 Symposium on VLSI Circuits Digest of Technical Papers

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This paper presents a self-aware processor with energy monitoring circuits that can measure actual energy consumption of the key blocks. The monitors are embedded into on-chip DC/DC converters and generate results within 10% of accuracy with minimal power (<0.1%) and area (<1%) overhead. Our system, which is implemented in 0.18μm technology, is designed to be voltage scalable from 1.8V down to 0.6V. Low-voltage SRAM operation is made possible through the use of 8T bit-cells and write-assists. The d-caches are designed to be re-configurable in associativity and size to adapt to compute-versus cache-bound phases of applications. Cache configuration is performed in < 3 clock cycles including tag invalidation. These hardware features enable a software self-aware computation engine (SEEC) to dynamically adapt the processor to meet performance and energy goals. Measurement results show that up to 8.4× energy savings can be achieved with DVFS and self-adaptation.

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“…In sub-or near-threshold operations, transistor current is extremely sensitive to process, voltage and temperature (PVT) variations. Then, read and write stabilities of the conventional 6T SRAM become very poor at their worst PVT corners [4]. In the 6T SRAM, read and write stabilities have contradicting design requirements [5], making it difficult to improve these stabilities at the same time.…”

mentioning

confidence: 99%

0.2 V 8T SRAM With PVT-Aware Bitline Sensing and Column-Based Data Randomization

Tuan

Lee

Wang

et al. 2016

IEEE J. Solid-State Circuits

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In sub/near-threshold operation, SRAMs suffer from considerable bit-line swing degradation when the data pattern of a column is skewed to "1" or "0". The worst scenariosregarding this problemoccur when the currently readSRAM cell has different data compared to the rest cells onthe same column. In this work, we overcome this challenge by using a column-based randomization engine(CBRE).ThisCBREcircuit randomizesdata stored to SRAM. This makes distribution of "1" and "0" in each column close to 50%, significantlyincreasingbit-line swing. To further improve the bit-line swing, we employ bit-line boost biasing and dynamic bit-line keeper schemes. Based on the mentioned techniques, we fabricateda 256 rows × 128 columns (32Kb)8T SRAM array in 65 nm CMOS technology.In our silicon measurement, the SRAM array shows successful 200mVoperation at room temperate, where energy consumption and access time are1 pJ and 2.5 µs, respectively.

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An embedded energy monitoring circuit for a 128kbit SRAM with body-biased sense-amplifiers

Cited by 5 publications

References 8 publications

A 9 T SRAM cell with data-independent read bitline leakage and improved read sensing margin for low power applications

A 9 T SRAM cell with data-independent read bitline leakage and improved read sensing margin for low power applications

A self-aware processor SoC using energy monitors integrated into power converters for self-adaptation

0.2 V 8T SRAM With PVT-Aware Bitline Sensing and Column-Based Data Randomization

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