A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os

Farjad-Rad, R.; Nguyen, An; Tran, J.; Greer, Thomas H.; Poulton, John W.; Dally, William J.; Edmondson, John H.; Senthinathan, R.; Rathi, R.; Lee, M.-J.E.; Ng, Hiok-Tiaq

doi:10.1109/jssc.2004.831457

Cited by 35 publications

(8 citation statements)

References 13 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…(8) The jitter transfer function is proportional to the reciprocal of the phase error transfer function and is given in (9). Although any target may be used, here we chose to use a target bit error rate (BER) of 10 for which is appropriate.…”

Section: Linearized Analysis Of Sample Systemmentioning

confidence: 99%

A digital clock and data recovery architecture for multi-gigabit/s binary links

Sonntag

Stonick

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005.

View full text Add to dashboard Cite

Abstract-In this tutorial paper, we present a general architecture for digital clock and data recovery (CDR) for high-speed binary links. The architecture is based on replacing the analog loop filter and voltage-controlled oscillator (VCO) in a typical analog phase-locked loop (PLL)-based CDR with digital components. We provide a linearized analysis of the bang-bang phase detector and CDR loop including the effects of decimation and self-noise. Additionally, we provide measured results from an implementation of the digital CDR system which are directly comparable to the linearized analysis, plus measurements of the limit cycle behavior which arises in these loops when incoming jitter is small. Finally, the relative advantages of analog and digital implementations of the CDR for high-speed binary links is considered.Index Terms-Clock and data recovery (CDR), clock recovery, digital phase-locked loop (DPLL), jitter.

show abstract

Section: Linearized Analysis Of Sample Systemmentioning

confidence: 99%

A digital clock and data recovery architecture for multi-gigabit/s binary links

Sonntag

Stonick

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005.

View full text Add to dashboard Cite

show abstract

“…Recently, multiplying delay-locked loop (MDLL) [3,4] based frequency multipliers have been introduced to replace PLL-based ones due to their advantages such as ease of design, smaller area, lower power dissipation, nostability issue, and better jitter performance. However, conventional MDLLs [3,4] suffer from a harmonic locking problem.…”

Section: Introductionmentioning

confidence: 99%

“…However, conventional MDLLs [3,4] suffer from a harmonic locking problem. Harmonic locking occurs when the DLL and MDLL locks to harmonic reference edges of the input clock as shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

A Reset-Free Anti-Harmonic Programmable MDLL-Based Frequency Multiplier

Park¹,

Kim²,

Kim³

2013

JSTS:Journal of Semiconductor Technology and Science

View full text Add to dashboard Cite

Abstract-A reset-free anti-harmonic programmable multiplying delay-locked loop (MDLL) that provides flexible integer clock multiplication for high performance clocking applications is presented. The proposed MDLL removes harmonic locking problems by utilizing a simple harmonic lock detector and control logic, which allows this MDLL to change the input clock frequency and multiplication factor during operation without the use of start-up circuitry and external reset. A programmable voltage controlled delay line (VCDL) is utilized to achieve a wide operating frequency range from 80 MHz to 1.2 GHz with a multiplication factor of 4, 5, 8, 10, 16 and 20. This MDLL achieves a measured peak-to-peak jitter of 20 ps at 1.2 GHz.

show abstract

“…Examples of these applications are clock multiplication and distribution, direct digital frequency synthesizers (DDS), data sampling and processing in high-speed serial links, memory interfaces, and Time-to-Digital Converters (TDCs) [1]- [4]. A better time resolution in multiphase clock generation is a constantly increasing need in these applications.…”

Section: Introductionmentioning

confidence: 99%

Self-adjusting multiple-period locked delay line For high-resolution multiphase clock generation

Baronti¹,

Lunardini²,

Roncella³

et al. 2005

2005 12th IEEE International Conference on Electronics, Circuits and Systems

View full text Add to dashboard Cite

We present a novel Delay-Locked Loop (DLL) based architecture for multiphase clock generation with a time resolution finer than the gate delay. The basic idea consists in locking the delay line to a certain multiple of clock periods that is not fixed a priori, but is self-adjusted depending on process and operating conditions, and working frequency. In such a way, a wide locking range is achieved with a very compact delay cell structure. The circuit has been used to design a new TDC architecture in which a resolution (time-bin size) of about 16 ps is reached using a 0.35 J..lm CMOS technology. Post-layout simulations show the feasibility of the technique.

show abstract

A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os

Cited by 35 publications

References 13 publications

A digital clock and data recovery architecture for multi-gigabit/s binary links

A digital clock and data recovery architecture for multi-gigabit/s binary links

A Reset-Free Anti-Harmonic Programmable MDLL-Based Frequency Multiplier

Self-adjusting multiple-period locked delay line For high-resolution multiphase clock generation

Contact Info

Product

Resources

About