A 33Mpixel 120fps CMOS image sensor using 12b column-parallel pipelined cyclic ADCs

Watabe, Toshihisa; Kitamura, Keiichi; Sawamoto, Takehide; Kosugi, Tadayoshi; Akahori, Tomoyuki; Iida, Takuya; Isobe, Keigo; Watanabe, Takashi; Shimamoto, Hiroshi; Ohtake, Hiroshi; Aoyama, Satoshi; Kawahito, Shoji; Egami, Norifumi

doi:10.1109/isscc.2012.6177047

Cited by 40 publications

(14 citation statements)

References 3 publications

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“…Both use the same ISD-ADC-based readout. According to (3) and (6), the settling time of a standard CIS architecture increases as the pixel pitch increases, reducing its frame rate. In contrast, the frame rate of the stacked architecture improves with the increase of the pixel pitch as the parallelism improves as well.…”

Section: B Frame Rate Analysismentioning

confidence: 99%

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A Low-Noise High-Frame-Rate 1-D Decoding Readout Architecture for Stacked Image Sensors

2014

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The continuously increasing array resolution of CMOS imagers poses a great challenge in combining highframe-rate and low light detection in the same sensor. To cope with this, parallel readout architectures are needed. This paper proposes a readout architecture for 8K stacked image sensors, which uses a novel 1D decoding readout based on block-of-pixels and incremental-sigma-delta ADCs. The proposed 1D decoding system reduces the control lines of the pixels and allows a simpler decoding, an increased parallelism, and an improved robustness over process yield. The experimental results from a test chip implemented in a standard CIS technology show that at 10 μm pixel pitch, the proposed readout architecture can achieve a highframe-rate of 730 frames/s and a low read noise of 1.4 e − . In a real stacked implementation, the frame rate can further increase to about 960 frames/s at 8K resolution, at the cost of a slight increase in thermal noise by 14 μV.Index Terms-Image sensor, UHDTV, dynamic range, low noise, high frame rate, 3-D integration, stacked, high resolution, ADC, incremental .

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Section: B Frame Rate Analysismentioning

confidence: 99%

“…This perception gave rise to the pixel race [2] where the pixel pitch continuously reduces and the pixel count increases. 4K TVs are available today and will be followed by 8K UHDTV (7680 × 4320 pixels) in the coming years [3]. Together with the spatial resolution increase, there is also need for low-light detection and high frame rate.…”

Section: Introductionmentioning

confidence: 99%

A Low-Noise High-Frame-Rate 1-D Decoding Readout Architecture for Stacked Image Sensors

2014

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“…For instance, in ultra-high-definition television (UHDTV) broadcasting, a 33 Mpixel (8k4k) CMOS image sensor with 12-bit ADC resolution at 120 fps has been developed. A column-parallel ADCs is the key element for the CMOS image sensor to realize the high pixel rate [1,2,3]. However the power consumption, which determines dark current noise, is still greater than 2W and the pixel pitch of 2.8 μm is quite large compared with the state-of-the-art pixel size.…”

Section: Introductionmentioning

confidence: 99%

A distributed ramp signal generator of column-parallel single-slope ADCs for CMOS image sensors

Imai

Yasutomi

Kagawa

et al. 2012

IEICE Electron. Express

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This paper proposes a distributed ramp signal generator of column-parallel single-slope ADCs for CMOS image sensors. This architecture does not require any power-hungry amplifiers of the conventional one but consists of miniaturized column-wise ramp signal generators connected together by metal wires, which achieves high linearity and high uniformity. Simulation results show less than 1LSB nonlinear error of the ramp signal at 12-bit ADC resolution is attained only by having the consumption current of 6.4 mA and the area of 2.4 mm 2 which are much smaller than the conventional one. It is also confirmed that 100 mΩ resistive connection attains less than 1LSB gain error mismatching, even though the mismatch of the column-wise ramp signal generators is as large as 20%.

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“…To realize 8K video cameras, 33Mpixel sensors [1][2] and a full-resolution camera system that uses three 33Mpixel sensors [3] have been reported. However, the weight of the camera with three sensors is over 40kg because the camera requires a large-format color-separation prism.…”

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confidence: 99%

6.2 133Mpixel 60fps CMOS image sensor with 32-column shared high-speed column-parallel SAR ADCs

Funatsu¹,

Huang²,

Yamashita³

et al. 2015

2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers

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To realize next-generation highly realistic sensation broadcasting systems, the research and development of 8K ultrahigh-definition television (UHDTV) systems have been promoted. To realize 8K video cameras, 33Mpixel sensors [1-2] and a full-resolution camera system that uses three 33Mpixel sensors [3] have been reported. However, the weight of the camera with three sensors is over 40kg because the camera requires a large-format color-separation prism. To reduce the size of the camera, single-chip imaging is a promising approach, and a compact single-chip 8K camera that weighs only 2kg has already been developed using a color 33Mpixel CMOS image sensor [4]. However, a conventional single-chip camera has a lower image quality than a full-resolution camera because the total pixel count of the single-sensor camera is only one-third of that of the three-sensor camera, and pixel interpolation is required to configure a full-resolution image. In this paper, a 133Mpixel sensor that can be operated at 60fps to realize a full-resolution 8K single-chip camera is described. To achieve both high speed and suitable ADC resolution, 32-column multiplexing analog readout circuitry and 14b high-speed redundant successive approximation register (SAR) ADCs [5] are adopted. As a result, a full-size image with a data rate of 128.71Gb/s at 60fps has been captured. Figure 6.2.1 shows the sensor block diagram. The total pixel array size is 15488(H) × 8776(V) including optical black pixels. The pixel design is a 2.45μm two-way vertically shared pinned photodiode. The readout of the array is addressed one physical pixel row at a time with 15,488 readout columns split between the top and bottom of the pixel array. The column readout circuit consists of a source-follower bias current (VLN), a programmable-gain amplifier (PGA), and two sets of sample-and-hold capacitor banks (SHCaps) for even-and-odd-row ping-pong operation. Analog data stored in the SHCaps are read out in parallel by 484 SAR-ADCs. Each SAR-ADC serially multiplexes 32 columns, and the resulting converter data are written into the SRAM line memory. Two banks of SRAM memory are used to provide pipelining of the ADC and SRAM readout to reduce the row time. The SRAM readout is further divided into 16 parallel ports to reduce the data rate. Each readout port outputs 960 columns, with the exception of the 4 edge corner ports that output an additional 32 optical black columns. CML output drivers are used to output 7b-wide data to a 574.56MHz DDR, achieving an aggregate data rate of 128.71Gb/s. The sensor block diagram is completed with distributed PLLs, SPI communication, and on-chip timing control logic. Figure 6.2.2 shows a simplified block diagram of the signal readout path and timing control logic blocks. The PGA, SHCaps, CMR, and ADC are similar to those described in [5], which enables us to design a large-format sensor at 60fps that fits into a 1D stitching reticle. Front-end multiplexing of the columns is optimized for 32 columns per CMR and a 14b SAR-ADC with a conversion r...

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A 33Mpixel 120fps CMOS image sensor using 12b column-parallel pipelined cyclic ADCs

Cited by 40 publications

References 3 publications

A Low-Noise High-Frame-Rate 1-D Decoding Readout Architecture for Stacked Image Sensors

A Low-Noise High-Frame-Rate 1-D Decoding Readout Architecture for Stacked Image Sensors

A distributed ramp signal generator of column-parallel single-slope ADCs for CMOS image sensors

6.2 133Mpixel 60fps CMOS image sensor with 32-column shared high-speed column-parallel SAR ADCs

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