A 34 MB/s MLC Write Throughput 16 Gb NAND With All Bit Line Architecture on 56 nm Technology

Cernea, Raul; Pham, Long; Moogat, Farookh; Chan, Siu‐Wai; Le, Binh; Li, Yan; Tsao, Shouchang; Tseng, Tsun-Ming; Nguyen, Khanh; Li, J.; Hu, Jianghai; Yuh, J.; Hsu, Cheng‐Hsing; Zhang, Fanglin; Kamei, Takeshi; Nasu, Hiroaki; Kliza, P.; Htoo, Khin; Lutze, J.; Yan, Dong; Higashitani, M.; Yang, Jiangang; Lin, Hongwei; Sakhamuri, V.; Li, A.; Pan, Feng; Yadala, S.; Subodh, Taigor; Pradhan, K P; Lan, J.; Chan, James; Abe, T.; Fukuda, Yasushi; Mukai, Hideo; Kawakami, Koichi; Liang, Chenju; Ip, T.; Chang, Shu-Fen; Lakshmipathi, J.; Huynh, Sharon; Pantelakis, D.; Mofidi, M.; Quader, K.

doi:10.1109/jssc.2008.2007152

Cited by 67 publications

(21 citation statements)

References 4 publications

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“…A wordline typically spans 32k to 64k cells. Our experimental flash designs use an all-bit-line (ABL) architecture wherein all the cells on the same wordline are read and programmed as a group [11] to achieve high performance as more cells can be programmed or read simultaneously. In a 2-bit MLC ABL design, all the least significant bits (LSB) on a wordline form what is called the LSB page and all the most significant bits (MSB) form the MSB page.…”

Section: A All Bit Line (Abl) Flashmentioning

confidence: 99%

Program interference in MLC NAND flash memory: Characterization, modeling, and mitigation

Cai

Mutlu

Haratsch³

et al. 2013

2013 IEEE 31st International Conference on Computer Design (ICCD)

169

200

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Abstract-As NAND flash memory continues to scale down to smaller process technology nodes, its reliability and endurance are degrading. One important source of reduced reliability is the phenomenon of program interference: when a flash cell is programmed to a value, the programming operation affects the threshold voltage of not only that cell, but also the other cells surrounding it. This interference potentially causes a surrounding cell to move to a logical state (i.e., a threshold voltage range) that is different from its original state, leading to an error when the cell is read. Understanding, characterizing, and modeling of program interference, i.e., how much the threshold voltage of a cell shifts when another cell is programmed, can enable the design of mechanisms that can effectively and efficiently predict and/or tolerate such errors.In this paper, we provide the first experimental characterization of and a realistic model for program interference in modern MLC NAND flash memory. To this end, we utilize the read-retry mechanism present in some state-of-the-art 2Y-nm (i.e., 20-24nm) flash chips to measure the changes in threshold voltage distributions of cells when a particular cell is programmed. Our results show that the amount of program interference received by a cell depends on 1) the location of the programmed cells, 2) the order in which cells are programmed, and 3) the data values of the cell that is being programmed as well as the cells surrounding it. Based on our experimental characterization, we develop a new model that predicts the amount of program interference as a function of threshold voltage values and changes in neighboring cells. We devise and evaluate one application of this model that adjusts the read reference voltage to the predicted threshold voltage distribution with the goal of minimizing erroneous reads. Our analysis shows that this new technique can reduce the raw flash bit error rate by 64% and thereby improve flash lifetime by 30%. We hope that the understanding and models developed in this paper lead to other error tolerance mechanisms for future flash memories.

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Section: A All Bit Line (Abl) Flashmentioning

confidence: 99%

Program interference in MLC NAND flash memory: Characterization, modeling, and mitigation

Cai

Mutlu

Haratsch³

et al. 2013

2013 IEEE 31st International Conference on Computer Design (ICCD)

169

200

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“…11 and 12 representing Ladder CP (Bender, 1994;Seeman and Sanders, 2008;Bazzini et al, 2012), Fibonacci CP (Ueno et al, 1991;Makowski and Maksimovic, 1995;Seeman and Sanders, 2008;Allasasmeh and Gregori, 2011;Gupta et al, 2013), Exponential CP (Cernea et al, 2009;Allasasmeh and Gregori, 2011) and a recently patented Tree Topology CP (Lu et al, 2010;Roy et al, 2014) respectively. As stated in (Seeman and Sanders, 2008), Series Parallel CP performs better in a capacitor limited process with impedance inversely proportional to frequency while the Dickson and Ladder CP (Fig.…”

Section: Miscellaneous Charge Pumpsmentioning

confidence: 99%

“…Fibonacci CPs (Ueno et al, 1991;Allasasmeh and Gregori, 2011;Gupta et al, 2013) and voltage doublers (Seeman and Sanders, 2008) are categorized as exponential or non-linear CPs. Figure 12a shows an Exponential CP applied to a Flash memory (Cernea et al, 2009) with reduced area and 50% lower internal impedances for the same pumping capabilities of past topologies. Chang and Hu (2006) proposed their Exponential CPs (Fig.…”

Section: Miscellaneous Charge Pumpsmentioning

confidence: 99%

“…These recent CP topologies have advanced towards body-biasing (Zhang and Lee, 2013;Peng et al, 2014;Kim et al, 2015;Ashraf and Masuomi, 2016) and gate controls (Shih and Otis, 2011;Zhang and Lee, 2013) for VCE enhancements of ~86% (180 mV) in Kim et al (2015) structure and ~93% (350 mV) in Shih and Otis (2011) Bootstrap CP design. (Cernea et al, 2009) (b) exponential-gain structure (Chang and Hu, 2006) (c) Tree-topology (Lu et al, 2010;Roy et al, 2014) In a nutshell, current CP design trends tend towards the lower power spectrum with prominence given to V TH cancellation schemes, RC delay reduction and raising of on/off current ratio (DBB schemes) when considering CP design metrics trade-offs in LV operations. …”

Section: Miscellaneous Charge Pumpsmentioning

confidence: 99%

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Review of Charge Pump Topologies for Micro Energy Harvesting Systems

Mi¹,

Islam

Sampe

et al. 2016

American Journal of Applied Sciences

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This paper reviews CMOS based charge pump topologies used within autonomous embedded micro-systems. These charge pump structures have evolved from its simplistic diode-tied, single-branches with major threshold drops to exponential type, dual-branches with sophisticated gate and substrate control for lower voltage operation. Published charge pumps are grouped based on architecture, operation principles and pump optimization techniques with their pros and cons compared and results contrasted. The various charge pump topologies and schemes used are considered based on pumping efficiency, power efficiency, charge transferability, circuit complexity, pumping capacitors, form factor and minimum supply voltages with an optimum load. This article concludes with an overview of suitable techniques and recommendations that will aid a designer in selecting the most suitable charge pump topology especially for low ambient micro energy harvesting applications.

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“…Because the WL-set and CSL are shared by all NSs in a VGU, commonly used forward-read schemes [22]- [24] in NAND flash are unable to achieve layer-awaresensing. In contrast, in reverse read/sensing schemes the cell threshold voltage is determined by the voltage between the word-line (WL) and bit-line (BL).…”

Section: ) Operation Of La-pv-rmentioning

confidence: 99%

Layer-Aware Program-and-Read Schemes for 3D Stackable Vertical-Gate BE-SONOS NAND Flash Against Cross-Layer Process Variations

Hung

Chang

Yang

et al. 2015

IEEE J. Solid-State Circuits

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3D vertical-gate (3DVG) NAND flash is a promising candidate for next-generation high-density nonvolatile memory. Cross-layer process variation renders 3DVG NAND susceptible to decreased speeds, yield, and reliability. This can be attributed to (a) cross-layer mismatch in bitline capacitance ( ), (b) the need for long program cycles, and (c) sensing-margin (SM) loss induced by the effects of background-pattern-dependency (BPD). This study proposes three circuit-level techniques to overcome these issues by employing the following: (1) distributed NAND-string scramble (DNSS), (2) layer-aware program-verify-and-read (LA-PV-R), and (3) a layer-aware-bitline-precharge (LA-BP) scheme. For an 8-layer 3DVG with 200 mV cross-layer mismatch in cell threshold voltage ( ), DNSS reduces the cross-layer -mismatch by 41%, LA-PV-R using various program-threshold-voltages ( ) for each layer enables a 25% reduction in the number of program cycles, and LA-BP succeeds in reducing BPD-induced SM loss by 56%. A 2-layer 3DVGNAND testchip and 8-layer testkey were fabricated to evaluate the proposed methods. The LA-PV-R and LA-BP have achieved a 0.75 V difference in between layer-0 and layer-1 with a 0.4V difference in BL clamping bias voltages and the LA-BP scheme has achieved a 44% reduction in BPD-induced SM loss. The three proposed schemes incur an area penalty of less than 0.1% in a Gb-scale 3DVG NAND device.

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A 34 MB/s MLC Write Throughput 16 Gb NAND With All Bit Line Architecture on 56 nm Technology

Cited by 67 publications

References 4 publications

Program interference in MLC NAND flash memory: Characterization, modeling, and mitigation

Program interference in MLC NAND flash memory: Characterization, modeling, and mitigation

Review of Charge Pump Topologies for Micro Energy Harvesting Systems

Layer-Aware Program-and-Read Schemes for 3D Stackable Vertical-Gate BE-SONOS NAND Flash Against Cross-Layer Process Variations

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