A 3D NAND Flash Ready 8-Bit Convolutional Neural Network Core Demonstrated in a Standard Logic Process

Kim, M.; Liu, M.; Everson, Luke; Park, G.; Jeon, Young Ho; Kim, S.; Lee, S.; Song, Sang-Bin; Kim, C. H.

doi:10.1109/iedm19573.2019.8993574

Cited by 18 publications

(4 citation statements)

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“…BEST LITHOGRAPHY CONDITION FOR STAIRCASE Fig. (5) shows that the distance between SS1 and SS0 increases with the exposure energy during lithography in 39 layers of staircase. The step of the energy matrix is 1.5 mJ/cm 2 .…”

Section: Resultsmentioning

confidence: 99%

An Improved Dimensional Measurement Method of Staircase Patterns With Higher Precision in 3D NAND

et al. 2020

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3D NAND is a great architectural innovation in the field of flash memory. The staircase for control gate is a unique and important process in the manufacturing of 3D NAND. The staircase is employed to form the electrical connection between the control gate and contact. The current method used to measure the dimension of staircase patterns is, however, not precise enough for the development of state-of-the-art 3D NAND. In this circumstance, an accurate measurement of dimension for as-formed staircase patterns is of great importance and technical interest. In this paper, an improved measurement method is proposed to meet the requirement for higher precision. By taking the overlay into account, a calculation formula for measuring the dimensional error of as-formed staircase is derived for the first time. Two kinds of anchor design (convex SS0 and concave SS0) are put forward to perform dedicated experiments. Achieved results show that the measurement error of as-formed staircase using this improved method is improved from 31.6 nm for normal measurement method to 14.1 nm. The dimensional uniformity of as-formed staircase is therefore improved significantly which in turn leads to well controlled word line leakage. Furthermore, in advanced staircase structure of stair divided scheme (SDS), the convex SS0 shows an advantage in cost compared to the concave SS0.INDEX TERMS 3D NAND, staircase, large dimension measurement, high precision.

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Section: Resultsmentioning

confidence: 99%

An Improved Dimensional Measurement Method of Staircase Patterns With Higher Precision in 3D NAND

et al. 2020

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“…In-memory comput-078504-17 ing, a non-von Neumann computing architecture, exhibits superior computational performance because it breaks through the limitations of memory wall by completely eliminating the energy and time required for data transport. Hardware demonstrations of different memory technologies have made remarkable progress (Table 2) [21,24,130,138,144,148,149,[178][179][180][181][182] in the realization of in-memory computing as reviewed in this article. Emerging resistive switch memory plays an increasingly important role in the post-Moore era due to its simple structure and rich functional characteristics in computing.…”

Section: Discussionmentioning

confidence: 99%

“…Stochastic generation Hybrid precision digital computing State-of-the-art hardware implementations in terms of different applications Stanford's 148 TOPS/W 65K RRAM neurosynaptic core [178] TRNG: Tohoku Uni./Purdue's stochastic MJTs [138] Binary logic: Peking Uni. 's 3M1R reconfigurable logic [144] Tsinghua's multiple RRAM arrays CNN system [24] Tsinghua's analog RRAMbased TRNG [181] POLIMI's RRAM stateful network logic [21] UMN's 3D NAND Flash 8-bit CNN core [179] PUF: UCSB's 4K RRAM fixed-resistance PUF [182] Multiple states: IBM's PCM correlation detection computing [148] Princeton's 658 TOPS/W SRAM CNN accelerator [180] Tsinghua's reconfigurable RRAM PUF [130] IBM's PCM mixed-precision computing [149]…”

Section: Neural Networkmentioning

confidence: 99%

In-memory computing to break the memory wall*

Huang¹,

Liu²,

Jiang³

et al. 2020

Chinese Phys. B

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Facing the computing demands of Internet of things (IoT) and artificial intelligence (AI), the cost induced by moving the data between the central processing unit (CPU) and memory is the key problem and a chip featured with flexible structural unit, ultra-low power consumption, and huge parallelism will be needed. In-memory computing, a non-von Neumann architecture fusing memory units and computing units, can eliminate the data transfer time and energy consumption while performing massive parallel computations. Prototype in-memory computing schemes modified from different memory technologies have shown orders of magnitude improvement in computing efficiency, making it be regarded as the ultimate computing paradigm. Here we review the state-of-the-art memory device technologies potential for in-memory computing, summarize their versatile applications in neural network, stochastic generation, and hybrid precision digital computing, with promising solutions for unprecedented computing tasks, and also discuss the challenges of stability and integration for general in-memory computing.

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“…The flash memory is attracting much attention not only for the storage memory but for the analog memory of the neural network applications [1][2][3][4][5]. The charge-trapping (CT)-type metal-oxidenitride-oxide-Si (MONOS) nonvolatile memory (NVM) is suitable for high integration because of its thinner gate stack structure compared to the floating-gate (FG) type NVM.…”

Section: Introductionmentioning

confidence: 99%

Threshold Voltage Control for MONOS Nonvolatile Memory with High-k HfN/HfO<sub>2</sub> Stacked Layers for Analog Memory Application

Ohmi¹,

Pyo²

2021

MSF

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In this paper, we have investigated the threshold voltage (VTH) control of metal-oxide-nitride-oxide-Si (MONOS) nonvolatile memory (NVM) with high-k HfN/HfO2 stacked layers for analog memory application. The Si surface atomically flattening was found to significantly improve the VTH controllability of the MONOS NVM with high-k HfN/HfO2 stacked layers. The multi-level-cell (MLC) operation by controlling the program voltage at the source and drain was demonstrated utilizing MONOS NVM with high-k HfN/HfO2 stacked layers.

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A 3D NAND Flash Ready 8-Bit Convolutional Neural Network Core Demonstrated in a Standard Logic Process

Cited by 18 publications

References 0 publications

An Improved Dimensional Measurement Method of Staircase Patterns With Higher Precision in 3D NAND

An Improved Dimensional Measurement Method of Staircase Patterns With Higher Precision in 3D NAND

In-memory computing to break the memory wall*

Threshold Voltage Control for MONOS Nonvolatile Memory with High-k HfN/HfO<sub>2</sub> Stacked Layers for Analog Memory Application

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