A 4.06 mW 10-bit 150 MS/s SAR ADC With 1.5-bit/cycle Operation for Medical Imaging Applications

Abstract

This paper reports a 10-bit 150 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with binary-scaled redundancy-facilitated error correction technique. The proposed 1.5-bit/cycle technique with built-in capacitive digital-to-analog converter (CDAC) redundancy, corrects multiple erroneous decisions in a total of nine conversion cycles. The proposed binary-scaled redundancy provides a 12.5% error tolerance range for the incomplete CDAC voltage settling. The digital error-correction logic circuit presented uses a bitoverlap-and-add technique. The prototype chip was fabricated in 65-nm CMOS technology and occupies chip area of 0.038 mm 2 . It consumes 4.06 mW from a 1.2 V supply, achieving the Nyquist signal-to-noise-and-distortion ratio (SNDR) of 57.81 dB and the effective number of bits of 9.31-bit at an operating frequency of 150 MS/s, corresponding to the figure-of-merit of 42.6 fJ/ conversion-step.

Design of 150‐μV input‐referred voltage 1‐GHz comparison frequency dual offset cancelation comparator for pH biomarker system‐on‐chip

“…In order to reduce input referred voltage (noise) in comparator circuits, it often to design digitally time-sequence switch and very complex techniques to overcome the kickback noise and input offset voltage [38][39][40][41][42] in comparator, and assisted with calibration scheme. [43][44][45] The input referred offset variation due to the capacitive path from ion sensing to the input stage circuit in SoC can degrade the overall performance of the system, for example, the input referred offset voltage shifts the background reference voltage levels in ADC, and result in the erroneous conversion process. In order to reduce the input referred noise to raise the sensitivity for reading the tiny capacitance due to ion change, we proposed a dual offset cancelation double tail comparator shown in Figure 3, and implement this comparator in a SoC sensor array for pH biomarker measurement.…”

A 10 Bit 5 MS/s Column SAR ADC With Digital Error Correction for CMOS Image Sensors

“…In contrast, in the proposed design shown in Fig. 1, a 10 bit's ADC's accuracy requirement is ±1/2 11 •VREF and the 6-bit second stage (B6~B13) can quantize up to a total of ±1/2 5 •VREF, which could cover the non-ideal 5-bit first stage (B1~B5)'s quantization error (±1/2 5 •VREF). B5 and B6 shrinks the ADC gain by 31/32 and introduces no nonlinearity; and the same applies to B12 and B13.…”

“…This translates to a higher continuous column conversion rate, compared to previous publications [1]- [4]. SAR ADCs are known for their medium resolution, prominent area and power and they have been recently used for high speed applications ranging from a few tens to a few hundred megahertz [5]- [8], using DEC. An N bit accurate conventional SAR ADC operates as both an N bit ADC and an N bit charge balancing DAC, both of which have to meet the accuracy of N bit [8].…”

“…In contrast, in SAR ADCs with DEC [5][6]- [8], the DAC settling time could be less than -ln(1/2^(N+1))•τ [9], which is required for a conventional counterpart, while τ being the product of RC of the DAC. DEC is generally based on the principle that if a comparator misjudges in a step, either due to comparator dynamic offset or incomplete settling, the following steps could correct for the misjudge: given that in each step, the DAC increases or decreases the charge balancing node voltage in an amount (Δ %) proportionally less than that in a conventional counterpart.…”

Exploiting uncertain timing information in time‐based SAR ADCs

“…The proposed approach, shares a similarity with multi-bit per step techniques that have been developed for SAR ADCs [3,[12][13][14][15][16][17][18][19][20][21][22][23][24][25][26] in the aspect of conducting multiple comparisons within one conversion cycle. The difference between this approach and the existing multi-bit per step techniques are the following.…”