A 4.2 mW 50 MS/s 13 bit CMOS SAR ADC With SNR and SFDR Enhancement Techniques

Miki, Takuji; Matsukawa, Takashi; Matsukawa, Kazuo; Bando, Yoji; Okumoto, Takeshi; Okihara, Koji; Sakiyama, Shiro; Dosho, Shiro

doi:10.1109/jssc.2015.2417803

Cited by 75 publications

(25 citation statements)

References 13 publications

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“…This approach not only improves ADC irrational characteristics of the dithering technique, but also does not deteriorate other performance of the ADC because of the superimposed large amplitude noise signal in the input signal [9].…”

Section: Dithering Techniquementioning

confidence: 99%

Research on broadband dither technique in signal acquisition

Tong

Chen

2019

J. eng.

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Section: Dithering Techniquementioning

confidence: 99%

Research on broadband dither technique in signal acquisition

Tong

Chen

2019

J. eng.

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“…A gain error of 0.6% is obtained after simulation of this circuit at 25 • C, which is relatively acceptable. A very high slew rate is achieved by this modified design that is 839 V/µs that will eventually lead to a very high speed of comparison and, thus, this comparator can be utilized in designing high-speed analog circuits, such as ADCs and DACs [30][31][32]. Table 4 summarizes the percentage variation of these parameters with temperature.…”

Section: = ( ) (µS) (µS)mentioning

confidence: 99%

An Improved CMOS Design of Op-Amp Comparator with Gain Boosting Technique for Data Converter Circuits

Khatak

Kumar

Dhull

2018

JLPEA

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A modified architecture of a comparator to achieve high slew rate and boosted gain with an improvement in gain design error is introduced and investigated in this manuscript. It employs the conventional architecture of common-mode current feedback with the modified gain booster topology to increase gain, slew rate, and reduced gain error from the conventional structure. Observation from the simulation results concludes that the modified structure using 24 transistors shows power dissipation of 362.29 μW in 90 nm CMOS technology by deploying a supply voltage of 0.7 V, which is a 70% reduction as compared to the usual common mode feedback (CMFD) structure. The symmetric slew rate of 839.99 V/µs for both charging and discharging is obtained, which is 173% more than the standard CMFD structure. A reduction of 0.61% in gain error is achieved through this architecture. A SPICE simulation tool based on 90 nm CMOS technology is employed for executing the Monte Carlo simulations. A brief comparison with earlier CMFD structures shows improved performance parameters in terms of power consumption and slew rate with the reduction in gain error.

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“…Recently, SAR algorithm based ADCs have also been used for higher speed and medium resolution applications by time interleaving multiple sub-SAR channels replacing traditionally implemented flash or pipeline structures [ 9 ]. However, with the increased number of bits, limitations due to comparator noise become severe which make SAR ADC as a difficult approach to implement for high resolution [ 10 , 11 ]. An energy-efficient prototype for high resolution is implemented front-end sampling switch, which results in eliminating the timing skew [ 12 ].…”

Section: Introductionmentioning

confidence: 99%

A Low-Power 12-Bit 20 MS/s Asynchronously Controlled SAR ADC for WAVE ITS Sensor Based Applications

Shehzad

Verma

Khan

et al. 2021

Sensors

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A low power 12-bit, 20 MS/s asynchronously controlled successive approximation register (SAR) analog-to-digital converter (ADC) to be used in wireless access for vehicular environment (WAVE) intelligent transportation system (ITS) sensor based application is presented in this paper. To optimize the architecture with respect to power consumption and performance, several techniques are proposed. A switching method which employs the common mode charge recovery (CMCR) switching process is presented for capacitive digital-to-analog converter (CDAC) part to lower the switching energy. The switching technique proposed in our work consumes 56.3% less energy in comparison with conventional CMCR switching method. For high speed operation with low power consumption and to overcome the kick back issue in the comparator part, a mutated dynamic-latch comparator with cascode is implemented. In addition, to optimize the flexibility relating to the performance of logic part, an asynchronous topology is employed. The structure is fabricated in 65 nm CMOS process technology with an active area of 0.14 mm2. With a sampling frequency of 20 MS/s, the proposed architecture attains signal-to-noise distortion ratio (SNDR) of 65.44 dB at Nyquist frequency while consuming only 472.2 µW with 1 V power supply.

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A 4.2 mW 50 MS/s 13 bit CMOS SAR ADC With SNR and SFDR Enhancement Techniques

Cited by 75 publications

References 13 publications

Research on broadband dither technique in signal acquisition

Research on broadband dither technique in signal acquisition

An Improved CMOS Design of Op-Amp Comparator with Gain Boosting Technique for Data Converter Circuits

A Low-Power 12-Bit 20 MS/s Asynchronously Controlled SAR ADC for WAVE ITS Sensor Based Applications

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