A 4.8 GS/s 5-bit ADC-Based Receiver With Embedded DFE for Signal Equalization

Varzaghani, A.; Yang, Chih-Kong Ken

doi:10.1109/jssc.2009.2013765

Cited by 30 publications

(6 citation statements)

References 28 publications

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“…When loop unrolling is employed, the magnitude comparator and slicer can be merged with the front-end ADC by replacing the ADC reference levels with the precalculated equalizer slicing levels [4,5,8,26]. Fig.…”

Section: Digital Equalizermentioning

confidence: 99%

ADC-Based Backplane Receivers: Motivations, Issues and Future

Chung¹

2016

JSTS:Journal of Semiconductor Technology and Science

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Abstract-The analog-to-digital-converter-based (ADCbased) backplane receivers that consist of a front-end ADC followed by a digital equalizer are gaining more popularity in recent years, as they support more sophisticated equalization required for high data rates, scale better with fabrication technology, and are more immune to PVT variations. Unfortunately, designing an ADC-based receiver that meets tight power and performance budgets of high-speed backplane link systems is non-trivial as both frontend ADC and digital equalizer can be power consuming and complex when running at high speed. This paper reviews the state of art designs for the front-end ADC and digital equalizers to suggest implementation choices that can achieve high speed while maintaining low power consumption and complexity. Design-space exploration using systemlevel models of the ADC-based receiver allows through analysis on the impact of design parameters, providing useful information in optimizing the power and performance of the receiver at the early stage of design. The system-level simulation results with newer device parameters reveal that, although the power consumption of the ADC-based receiver may not comparable to the receivers with analog equalizers yet, they will become more attractive as the fabrication technology continues to scale as power consumption of digital equalizer scales well with process.

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Section: Digital Equalizermentioning

confidence: 99%

ADC-Based Backplane Receivers: Motivations, Issues and Future

Chung¹

2016

JSTS:Journal of Semiconductor Technology and Science

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“…Some recent examples of ADCs with embedded equalization include [4] and [5]. In [4], FIR/IIR equalization is embedded in the cap-DAC of a successive approximation register (SAR) ADC through selective sampling, at the cost of reduced ADC conversion rate.…”

Section: Embedded Equalization In Adc-based Linksmentioning

confidence: 99%

“…In [4], FIR/IIR equalization is embedded in the cap-DAC of a successive approximation register (SAR) ADC through selective sampling, at the cost of reduced ADC conversion rate. The implementation in [5] embeds one tap of equalization into a 4.8GS/s pipelined ADC. However, for the resolutions typically required in high-speed I/O systems, pipeline architectures are generally not the power optimal choice.…”

Section: Embedded Equalization In Adc-based Linksmentioning

confidence: 99%

Embedded equalization for ADC-based serial I/O receivers

Shafik

Lee

Tabasy

et al. 2011

2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems

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“…To exceed 10GS/s, multiple ADCs are time-interleaved using multiple clock phases. By employing a high degree of interleaving, ADC architectures such as pipelined [6][9][10] [11] and successive-approximation (SAR) [12] have been shown to achieve multi-GS/s rates. The only circuit that needs to handle the full data rate is the sample/hold (S/H).…”

Section: A Sampling Rate and Interleavingmentioning

confidence: 99%

“…Because each stage of a pipelined architecture leaves a residue that only spans a fraction of the signal range, the reference levels are not fully programmable and hence cannot be used for a loop-unrolled architecture. Such a design have been shown to reach >1.5GS/s per interleaving path with FoM of 2 [11], 2.4 [10], and 0.6pJ/step [6] in 130nm, 90nm, and 65nm CMOS technology respectively. Interestingly, the stage-by-stage resolution of the input signal and the multi-cycle conversion delay enables an option of integrating a low tap-weight DFE at each stage [19].…”

Section: A Adc Architecturementioning

confidence: 99%

ADC-based serial I/O receivers

Yang¹,

Chen²

2009

2009 IEEE Custom Integrated Circuits Conference

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Fully digital receiver frontends have garnered interest for serial I/O receivers. While the speed and resolution are achievable in CMOS technologies, the challenge is to achieve low power dissipation so that the I/O links can be integrated in large ASICs. This paper describes different design techniques and shows that the power can be reduced by constraining the specifications and by making architectural trade-offs.

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A 4.8 GS/s 5-bit ADC-Based Receiver With Embedded DFE for Signal Equalization

Cited by 30 publications

References 28 publications

ADC-Based Backplane Receivers: Motivations, Issues and Future

ADC-Based Backplane Receivers: Motivations, Issues and Future

Embedded equalization for ADC-based serial I/O receivers

ADC-based serial I/O receivers

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