Abstract-A low-power receiver with a one-tap decision feedback equalization (DFE) was fabricated in 90-nm CMOS technology. The speculative equalization is performed using switched-capacitor-based addition at the front-end sample-hold circuit. In order to further reduce the power consumption, an analog multiplexer is used in the speculation technique implementation. A quarter-rate-clocking scheme facilitates the use of low-power front-end circuitry and CMOS clock buffers. The receiver was tested over channels with different levels of ISI. The signaling rate with BER 10 12 was significantly increased with the use of DFE for short-to medium-distance PCB traces. At 10-Gb/s data rate, the receiver consumes less than 6.0 mW from a 1.0-V supply. This includes the power consumed in all quarter-rate clock buffers, but not the power of a clock recovery loop. The input clock phase and the DFE taps are adjusted externally.

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Design of a high-speed low-to-medium resolution analogto-digital converter with closed-loop pipeline structure has been investigated. We demonstrate a single-path 6UOMSls, 5-bit ADC. It is optimally designed to meet the requirements of a serial-link receiver. For high input-bandwidth, total inputcapacitance is only 17Off. At high frequencies, to improve resolution beyond the amplifier-settling limit, the reference voltage of each pipeline-stage is digitally tuned. The chip is fabricated in 0.18pm CMOS technology and consumes 70mW at I .8V power-supply.

A low power receiver with a one tap DFE was fabricated in 90nm CMOS technology. The speculative equalization is performed using switched-capacitor-based addition directly at the front-end sample-hold circuit. In order to further reduce the power consumption, an analog multiplexer is used in the speculation technique implementation. A quarter-rateclocking scheme facilitates the use of low-power front-end circuitry and CMOS clock buffers. At 10Gb/s data rate, the receiver consumes less than 6.0mW from a 1.0V supply.