A 600MS/s, 5-bit pipelined analog-to-digital converter for serial-link applications

Varzaghani, A.; Yang, Chih-Kong Ken

doi:10.1109/vlsic.2004.1346585

Cited by 22 publications

(6 citation statements)

References 6 publications

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“…As stated previously, the speed of the latching comparator is determined mainly by its recovery time (t r ), which can be expressed by Eqn. (1)…”

Section: Comparator Designmentioning

confidence: 99%

“…High-speed, low-resolution analogue-to-digital converters (ADCs) have widespread applications in wired and wireless broadband communications [1], radar receivers [2], digital oscilloscopes [3] and millimetre arrays for radio astronomy [4]. The rapid scaling of transistor and interconnect dimensions has enabled increased chip complexity and performance.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

GHz Class Low-Power Flash ADC for Broadband Communications

Sexton

Tauqeer

Mohiuddin

et al. 2008

2008 International Conference on Advanced Semiconductor Devices and Microsystems

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A low-power (~400mW) high-speed (2-4GS/s) 4-bit Analogue-to-Digital Converter (ADC) based on InP/InGaAs heterojunction bipolar transistors (HBT)has IntroductionHigh-speed, low-resolution analogue-to-digital converters (ADCs) have widespread applications in wired and wireless broadband communications [1], radar receivers [2], digital oscilloscopes [3] and millimetre arrays for radio astronomy [4]. The rapid scaling of transistor and interconnect dimensions has enabled increased chip complexity and performance. In terms of CMOS for example, improvements in high-k dielectric materials have pushed this technology to approach a maximum speed 10-20GHz [5]. However, for ultra-low power designs, alternative materials, such as SiGe or III-V compound semiconductor technologies are the only viable option [5].For mixed-signal applications and high-speed digital logic design, closely matched devices are indispensable. The improved threshold voltage control of heterojunction bipolar transistors (HBT) compared to Field Effect Transistor (FET) devices, as well as their high linearity and fundamentally lower 1/f noise [6] make these an ideal choice. While SiGe HBTs can be used for speeds approaching 77GHz [5], its peak electron velocity occurs at a much higher electric field than InGaAs [7]. Hence to achieve comparable high-speed operation, SiGe HBTs require larger bias voltages which results in increased power dissipation. Also, the low bandgap InGaAs used in the base layer of InP/InGaAs or AlInAs/InGaAs HBTs reduce the turn-on voltage, and thus make these material systems suited for low-power applications.This paper presents the continuing research into developing an ultra-low power ADC based on InP/InGaAs HBTs. The ultimate achievement is to fabricate a 4-bit Flash ADC that operates with a sampling frequency of 2-4GHz, and dissipates less than 400mW. Material Growth and FabricationThe epitaxial layers (shown in Table 1) were grown on a VG 90H solid-source molecular beam Epitaxy (MBE) system on Fe-doped semi-insulating (100) InP substrates. Growth was performed at a relatively low temperature of ~420 o C and used stoichiometric conditions for both the Arsenide and Phosphide materials. Phosphorus was generated from a GaP decomposition source whose operational aspects are described elsewhere [8].

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“…As stated previously, the speed of the latching comparator is determined mainly by its recovery time (t r ), which can be expressed by Eqn. (1)…”

Section: Comparator Designmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

GHz Class Low-Power Flash ADC for Broadband Communications

Sexton

Tauqeer

Mohiuddin

et al. 2008

2008 International Conference on Advanced Semiconductor Devices and Microsystems

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“…Several works have reported on calibrating stage gain error in the analog domain. In [4], reference voltage in each pipeline stage is controlled to adjust stage gain. However, this technique is only applicable when the linear settling of the op-amp is guaranteed.…”

Section: Introductionmentioning

confidence: 99%

Design of Interpolated Pipeline ADC Using Low-Gain Open-Loop Amplifiers

Lee

Miyahara

Matsuzawa

2013

IEICE Trans. Electron.

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This paper describes the design of an interpolated pipeline analog-to-digital converter (ADC). By introducing the interpolation technique into the conventional pipeline topology, it becomes possible to realize a more than 10-bits resolution and several hundred MS/s ADC using low-gain open-loop amplifiers without any multiplying digital-to-analog converter (MDAC) calibration. In this paper, linearity requirement of the amplifier is analyzed with the relation of reference range and stage resolution first. Noise characteristic is also discussed with amplifier's noise bandwidth and load capacitance. After that, sampling speed and SNR characteristic are examined with various amplifier currents. Next, the resolution optimization of the pipeline stage is discussed based on the power consumption. Through the analysis, reasonable parameters for the amplifier can be defined, such as transconductance, source degeneration resistance and load capacitance. Also, optimized operating speed and stage resolution for interpolated pipelined ADC is shown. The analysis in this paper is valuable to both the design of interpolated pipeline ADCs and other circuits which incorporate interpolation and amplifiers.

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“…For low-resolution, GHz class ADCs both technologies are feasible [7][8][9][10][11][12][13] and have found widespread applications in radar receivers [11], digital oscilloscopes [10] and millimetre arrays for radio astronomy [12]. The maximum sampling rate of these ADCs can be enhanced either by utilising time-interleaved techniques [8] or using a process that offers faster devices (e.g.…”

Section: Introductionmentioning

confidence: 99%