A 4-<i>μ</i>m Diameter SPAD Using Less-Doped N-Well Guard Ring in Baseline 65-nm CMOS

Lu, Xin; Law, Man‐Kay; Yang, Ji; Zhao, Xiaojin; Mak, Pui-In; Martins, Rui P.

doi:10.1109/ted.2020.2982701

Cited by 17 publications

(6 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Since 12 SPAD Ising/Potts Solver illumination can easily be controlled across an entire chip but not locally, it is suitable for temperature control but not for controlling the rate of individual SPADs. Controlling the reverse bias can be done for each SPAD individually, but the effect of changing the SPAD bias is dependent on the exact SPAD design; some SPAD designs demonstrate bias effects exponentially altering the dark count rate [38],…”

Section: Variable-rate Spad Circuitsmentioning

confidence: 99%

CMOS-compatible Ising and Potts Annealing Using Single Photon Avalanche Diodes

Nelson

Theogarajan

2022

Preprint

View full text Add to dashboard Cite

Massively parallel annealing processors may offer superior performance for a wide range of sampling and optimization problems. A key component dictating the size of these processors is the neuron update circuit, ideally implemented using special stochastic nanodevices. We leverage photon statistics using single photon avalanche diodes (SPADs) and temporal filtering to generate stochastic states. This method is a powerful alternative offering unique features not currently seen in annealing processors: the ability to continuously control the computational temperature and the seamless extension to the Potts model, a n-state generalization of the two-state Ising model. SPADs also offer a considerable practical advantage since they are readily manufacturable in current standard CMOS processes. As a first step towards realizing a CMOS SPAD-based annealer, we have designed Ising and Potts models driven by an array of discrete SPADs and show they accurately sample from their theoretical distributions.

show abstract

Section: Variable-rate Spad Circuitsmentioning

confidence: 99%

CMOS-compatible Ising and Potts Annealing Using Single Photon Avalanche Diodes

Nelson

Theogarajan

2022

Preprint

View full text Add to dashboard Cite

show abstract

“…With a round-shaped active area SPAD, we obtain a diameter of about 14 µm: there is no advantage in using an SPAD with a diameter larger than 14 µm, while it could be possible to use smaller ones. Although SPADs with diameters narrower than 10 µm have been reported [25][26][27], they could suffer by a reduced actual PDP, due to edge effects and reduced fill-factor. With a 14 µm SPAD, the background photon rate is: Let us consider an SPAD with a typical PDP (Photon-Detection Probability) of 20% at the wavelength of interest (660 nm) [24] and the signal photon density of 3.4 × 10 4 ph/mm 2 per laser pulse and the ambient photon density of 2 × 10 12 ph/s/mm 2 , as computed in Section 2.…”

Section: Geometrical Considerationsmentioning

confidence: 99%

which is not negligible.…”

Section: Required Detector Performancementioning

confidence: 99%

“…However, by reducing the SPAD diameter below 14 µm, the number of SPADs per unit area can increase. The architectures analyzed in this section will consider 10 μm diameter SPADs, since smaller detectors would have worse performance and lower FF [ 25 , 26 , 27 ]. In this condition, by applying Equations (4) and (5), we obtain, respectively, 0.52 signal photons and 0.32 ambient photons hitting each 10 μm SPAD per pulse: therefore, in the worst case at the longer distance where the 0.32 ambient photons are hitting the SPAD before the laser pulse.…”

Section: Candidate Architecturesmentioning

confidence: 99%

See 1 more Smart Citation

Spot Tracking and TDC Sharing in SPAD Arrays for TOF LiDAR

Sesta

Severini

Villa

et al. 2021

Sensors

View full text Add to dashboard Cite

Light Detection and Ranging (LiDAR) is a widespread technique for 3D ranging and has widespread use in most automated systems that must interact with the external environment, for instance in industrial and security applications. In this work, we study a novel architecture for Single Photon Avalanche Diode (SPAD) arrays suitable for handheld single point rangefinders, which is aimed at the identification of the objects’ position in the presence of strong ambient background illumination. The system will be developed for an industrial environment, and the array targets a distance range of about 1 m and a precision of few centimeters. Since the laser spot illuminates only a small portion of the array, while all pixels are exposed to background illumination, we propose and validate through Monte Carlo simulations a novel architecture for the identification of the pixels illuminated by the laser spot to perform an adaptive laser spot tracking and a smart sharing of the timing electronics, thus significantly improving the accuracy of the distance measurement. Such a novel architecture represents a robust and effective approach to develop SPAD arrays for industrial applications with extremely high background illumination.

show abstract

“…To address this issue, a virtual guard ring has been employed in p þ ∕n-well SAPDs to achieve smaller structures. [13][14][15][16] In Refs. 13 and 16, the virtual guard ring is exploited between active area and STI to separate the edge of the STI from the avalanche region to reduce the dark count rate (DCR) induced by STI interface traps, which limits the fill-factor.…”

Section: Introductionmentioning

confidence: 99%

Experimental and simulation study of fill-factor enhancement using a virtual guard ring in n+/p-well CMOS single-photon avalanche diodes

et al. 2021

View full text Add to dashboard Cite

The use of a physical guard ring in CMOS single-photon avalanche diodes (SPADs) based on n þ /(deep)p-well and p þ /(deep)n-well structures is a common solution to control the electric field of the SPADs periphery and prevent the premature lateral breakdown. However, this leads to a decrease of the detection efficiency, i.e., the fill-factor, especially when the SPADs size is reduced. Our paper presents an experimental and simulation study on replacing the physical guard ring by a virtual guard ring to improve the fill-factor and the scalability of a n þ ∕p-well SPAD implemented in 0.35-μm pin-photodiode CMOS technology. Accordingly, the optimization of the virtual guard ring and its superiority at downscaling are discussed, and the SPAD scalability in size with respect to the fill-factor is quantified in this technology. © The Authors.Published by SPIE under a Creative Commons Attribution 4.0 Unported License. Distribution or reproduction of this work in whole or in part requires full attribution of the original publication, including its DOI.

show abstract

A 4-μm Diameter SPAD Using Less-Doped N-Well Guard Ring in Baseline 65-nm CMOS

Cited by 17 publications

References 8 publications

CMOS-compatible Ising and Potts Annealing Using Single Photon Avalanche Diodes

CMOS-compatible Ising and Potts Annealing Using Single Photon Avalanche Diodes

Spot Tracking and TDC Sharing in SPAD Arrays for TOF LiDAR

Experimental and simulation study of fill-factor enhancement using a virtual guard ring in n+/p-well CMOS single-photon avalanche diodes

Contact Info

Product

Resources

About