A $4 \times 4 \times 2$ Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links

Vivet, Pascal; Thonnart, Yvain; Lemaire, R.; Santos, Carla Eliete Iochims dos; Beigné, Edith; Bernard, Christian; Darve, Florian; Lattard, Didier; Miro-Panades, Ivan; Dutoit, Denis; Clermidy, Fabien; Chéramy, S.; Sheibanyrad, Abbas; Pétrot, Frédéric; Flamand, Éric; Michailos, Jean; Arriordaz, Alexandre; Wang, Lee; Schloeffel, J.

doi:10.1109/jssc.2016.2611497

Cited by 20 publications

(6 citation statements)

References 32 publications

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“…QDI AFIFOs are a quite efficient way to integrate complex IPs in both, intra-chip and extra-chip environments [8]. This work provides insights on how a set of the most used design choices of codes, protocols and ack generation can influence the performance of such AFIFOs.…”

Section: Discussionmentioning

confidence: 99%

“…Communication between chiplets in 3D IC stacks is better achieved using asynchronous communication, and QDI design is used here, as described e.g. by Vivet et al [8]. Complex ICs are often a collection of synchronous intellectual property modules (IPs), either acquired or developed inhouse, involving multiple teams and different design cultures.…”

Section: Introductionmentioning

confidence: 99%

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Quasi Delay Insensitive FIFOs: Design Choices Exploration and Comparison

Rodolfo

Sartori

Moreira³

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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This paper explores asynchronous FIFOs design choices, more specifically FIFOs from the quasi-delay insensitive (QDI) template family. It proposes eight different asynchronous FIFO structures on a CMOS 45nm technology, using a QDI standard cell library. Structures are exercised through analogmixed-signal simulation, ranging from nominal to subthreshold supply voltages. Follows a comparison of area, throughput and power efficiency. The experimental results allow inferring a technique for designers to select the most adequate QDI FIFO flavor for specific circuits. Insight on the experiments assesses the beneficial and/or limiting effects of using the specific cell library.

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Section: Discussionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Quasi Delay Insensitive FIFOs: Design Choices Exploration and Comparison

Rodolfo

Sartori

Moreira³

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…There exist only a limited number of works: Ref. [37] proposes a router architectures which is limited by the slower clock frequency for packets traveling along the asynchronous path. However, enabling asynchronous communication between routers is not a common topic due to its large overhead and limited practical relevance in homogeneous 3D systems.…”

Section: Related Workmentioning

confidence: 99%

NoCs in Heterogeneous 3D SoCs: Co-Design of Routing Strategies and Microarchitectures

et al. 2019

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Heterogeneous 3D System-on-Chips (3D SoCs) are the most promising design paradigm to combine sensing and computing within a single chip. A special characteristic of communication networks in heterogeneous 3D SoCs is the varying latency and throughput in each layer. As shown in this work, this variance drastically degrades the network performance. We contribute a co-design of routing algorithms and router microarchitecture that allows to overcome these performance limitations. We analyze the challenges of heterogeneity: Technology-aware models are proposed for communication and thereby identify layers in which packets are transmitted slower. The communication models are precise for latency and throughput under zero load. The technology model has an area error and a timing error of less than 7.4% for various commercial technologies from 90 to 28nm. Second, we demonstrate how to overcome limitations of heterogeneity by proposing two novel routing algorithms called Z + (XY)Z − and ZXYZ that enhance latency by up to 6.5× compared to conventional dimension order routing. Furthermore, we propose a high verticalthroughput router microarchitecture that is adjusted to the routing algorithms and that fully overcomes the limitations of slower layers. We achieve an increased throughput of 2 to 4× compared to a conventional router. Thereby, the dynamic power of routers is reduced by up to 41.1% and we achieve improved flit latency of up to 2.26× at small total router area costs between 2.1% and 10.4% for realistic technologies and application scenarios. INDEX TERMS 3D integrated circuits, network on chip, heterogeneous integration, monolithic stacking.

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“…The basic architecture of NoIF is based on UDs and the wide global links that enable communication between adjacent UDs. Existing NoC communication algorithms and architectures [10], [11] are exploited to enhance the basic architecture. Each die within the Si-IF that needs to communicate with another remotely placed die (not nearest neighbor) will utilize the NoIF.…”

Section: A Noif Architecturementioning

confidence: 99%

Network on interconnect fabric

Vaisband¹,

Bajwa²,

Iyer³

2018

2018 19th International Symposium on Quality Electronic Design (ISQED)

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Silicon interconnect fabric (Si-IF) supports integration of bare dies using thermal compression bonding on a Si wafer substrate. Fine pitch (2 to 10 µm) horizontal and vertical interconnects are feasible within the Si-IF using standard Si processing techniques. A network on interconnect fabric (NoIF) is proposed in this paper. The NoIF enables integration of ultra large scale heterogeneous systems within the technologically mature Si-IF platform. NoIF is based on utility dies which serve as intelligent nodes within the network. NoIF enables global communication, power conversion and management, synchronization, processing and memory capabilities, redundancy allocation, and test of the Si-IF, and the utility and functional dies.

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A $4 \times 4 \times 2$ Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links

Cited by 20 publications

References 32 publications

Quasi Delay Insensitive FIFOs: Design Choices Exploration and Comparison

Quasi Delay Insensitive FIFOs: Design Choices Exploration and Comparison

NoCs in Heterogeneous 3D SoCs: Co-Design of Routing Strategies and Microarchitectures

Network on interconnect fabric

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