A 40 Gb/s CMOS Serial-Link Receiver With Adaptive Equalization and Clock/Data Recovery

Abstract

This paper presents a 40 Gb/s serial-link receiver including an adaptive equalizer and a CDR circuit. A parallel-path equalizing filter is used to compensate the high-frequency loss in copper cables. The adaptation is performed by only varying the gain in the high-pass path, which allows a single loop for proper control and completely removes the RC filters used for separately extracting the high-and low-frequency contents of the signal. A full-rate bang-bang phase detector with only five latches is proposed in the following CDR circuit. Minimizing the number of latches saves the power consumption and the area occupied by inductors. The performance is also improved by avoiding complicated routing of high-frequency signals. The receiver is able to recover 40 Gb/s data passing through a 4 m cable with 10 dB loss at 20 GHz. For an input PRBS of 2 7 1, the recovered clock jitter is 0.3 ps rms and 4.3 ps pp . The retimed data exhibits 500 mV pp output swing and 9.6 ps pp jitter with BER 10 12 . Fabricated in 90 nm CMOS technology, the receiver consumes 115 mW, of which 58 mW is dissipated in the equalizer and 57 mW in the CDR.

A pattern-guided adaptive equalizer in 65nm CMOS

“…Figure 20.5.4 shows the implementation of the analog equalizer, which consists of three different paths in order to create the desired frequency response [5]. Two bandpass filters are followed by variable gain amplifiers (VGA) that allow independent gain control at f N and f N /2.…”

“…The controller is based on C1 instead of C2 because the former compensates for higher signal attenuation. After all three coefficients converge, the controllers lock them to their final values.Figure 20.5.4 shows the implementation of the analog equalizer, which consists of three different paths in order to create the desired frequency response [5]. Two bandpass filters are followed by variable gain amplifiers (VGA) that allow independent gain control at f N and f N /2.…”

On-chip data communication : analysis, optimization and circuit design

“…The first flavor is continuous-time equalization, with (HF) boosting circuits that compensate for the attenuation of the channel, also called 'linear equalization' [117,123,[125][126][127][128][129][130][131][132][133]. This flavor has the longest history and is still being used in many contemporary transceivers, but its popularity seems to diminish because of another equalization form, the so called 'Decision-feedback equalization' (DFE) [98, 111-116, 119, 134-138].…”

“…For continuous-time receiver equalizers, other adaptation algorithms have been used, for example methods that compare the energy in different frequency bands before and after the detector [125,128,129,131,133]. A similar method is to compare the slope before and after the detector [130].…”

“…In case of a continuous-time receiver equalizer, the CDR can simply be placed after the equalizer [131,133]. In this case, CDR operates on data patterns with well-defined edges, simplifying the clock recovery and enabling the use of classical phase detectors for plain binary (NRZ) data such as the Hogge [103] or Alexander [104] phase detector.…”