A 40 Mb/s soft-output Viterbi decoder

Joeressen, O.J.; Meyr, H.

doi:10.1109/4.391121

Cited by 17 publications

(8 citation statements)

References 20 publications

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“…This technique uses parallel read pointers to access as many independent banks of memory, while a write pointer simultaneously stores the decisions from the ACS recursions into a memory bank. An alternative [8] is to use a single bank of multiported DRAM.…”

Section: A Register-exchange and Memory-traceback Methodsmentioning

confidence: 99%

“…Both essentially examine a list of competing paths by retracing a history of decisions and path metric differences. Previous implementations of the SOVA used either the register-exchange method [8] or memory-traceback method [15].…”

Section: Survivor Path Decodingmentioning

confidence: 99%

“…An early VLSI implementation of a SOVA decoder [8] achieved 40 Mb/s throughput in a 1-m CMOS standard cell technology. In order to reduce the power and area of the implementation, RAM macros were used.…”

Section: Introductionmentioning

confidence: 99%

“…These steps permit the computations of the add and compare steps to be performed in parallel. The path selection mechanisms make use of a modified register-exchange [8] to avoid the throughput bottleneck in SRAM blocks.…”

Section: Introductionmentioning

confidence: 99%

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A 500-mb/s soft-output viterbi decoder

Yeo

Augsburger²,

Davis³

et al. 2003

IEEE J. Solid-State Circuits

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Abstract-Two eight-state 7-bit soft-output Viterbi decoders matched to an EPR4 channel and a rate-8/9 convolutional code are implemented in a 0.18-m CMOS technology. The throughput of the decoders is increased through architectural transformation of the add-compare-select recursion, with a small area overhead. The survivor-path decoding logic of a conventional Viterbi decoder register exchange is adapted to detect the two most likely paths. The 4-mm 2 chip has been verified to decode at 500 Mb/s with 1.8-V supply. These decoders can be used as constituent decoders for Turbo codes in high-performance applications requiring information rates that are very close to the Shannon limit.

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Section: A Register-exchange and Memory-traceback Methodsmentioning

confidence: 99%

Section: Survivor Path Decodingmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A 500-mb/s soft-output viterbi decoder

Yeo

Augsburger²,

Davis³

et al. 2003

IEEE J. Solid-State Circuits

View full text Add to dashboard Cite

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“…The datapath of turbo is less wide than that of Viterbi (8 vs. 64 or more states), but it has to run much faster because of the iterations (8 iterations assumed). In order to enable the turbo datapath to run at feasible clock speeds, multiple datapaths can be introduced, running multiple windows in parallel [7,8]. For such parallel window architectures, both the intermediate data memory and interleaver address LUT need to have sufficient number of banks.…”

Section: Datapath Considerationsmentioning

confidence: 99%

Scalable Reconfigurable Channel Decoder Architecture for Future Wireless Handsets

Krishnaiah

Engin

Sawitzki

2007

2007 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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The current trend in the consumer devices and communication service provider market is the integration of different communication standards within a single device (e.g. GSM phone with Bluetooth, WLAN and infrared interface) requiring tight integration of mobile broadcast, networking and cellular technologies within one product. Channel decoder is traditionally one of the most computationally intensive building block within digital receivers. The aim of this paper is to investigate the feasibility of a programmable channel decoder that can be dynamically reconfigured for decoding turbo and convolutionally encoded streams from various wireless standards. The architecture options are presented and the area costs and flexibility compared between the options. The resulting decoder architecture supports hardware resource sharing and reconfiguration between different standards and decoders and is more efficient in terms of silicon area than independent implementation of every decoder on the same IC.

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