A 40-mW 7-bit 2.2-GS/s Time-Interleaved Subranging CMOS ADC for Low-Power Gigabit Wireless Communications

Ku, I-Ning; Xu, Zhiwei; Kuan, Yen-Cheng; Wang, Yen-Hsiang; Chang, Mau-Chung Frank

doi:10.1109/jssc.2012.2196731

Cited by 29 publications

(7 citation statements)

References 18 publications

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“…In [14], the channel offset mismatches are calibrated through digital-controlled corrective current sources embedded in the track-and-hold amplifiers of the sub-ADC. In [15], the timing skew is detected in the digital domain by minimizing the cross-correlation between each sub-ADC and any additional calibration ADC.…”

Section: Mixed Calibration Techniquesmentioning

confidence: 99%

Mismatch calibration methods for high-speed time-interleaved ADCs

Bénabès

Lelandais-Perrault

Dortz

2014

2014 IEEE 12th International New Circuits and Systems Conference (NEWCAS)

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International audienceTime Interleaved ADCs (TIADCs) are a good solu-tion to implement high sampling rate converters at a moderate hardware cost. However, they suffer from mismatches between the ADC channels, such as offset, gain, timing skew and possibly bandwidth mismatches. These mismatches have to be corrected in order to get sufficient performances from the converter. This paper presents the classical calibration methods and focuses on the blind ones. Among those, both mixed analog-digital methods and fully digital methods are overviewed. By considering the state-of-the-art of published chips, a comparison between those methods is provided

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Section: Mixed Calibration Techniquesmentioning

confidence: 99%

Mismatch calibration methods for high-speed time-interleaved ADCs

Bénabès

Lelandais-Perrault

Dortz

2014

2014 IEEE 12th International New Circuits and Systems Conference (NEWCAS)

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“…Its fully digital method adds no extra clock jitter compared with digital detection and analog correlation, and is the adopted method in this work. For the channel ADC, a successive approximation register (SAR) is more attractive, due to its outstanding power efficiency [2,4,7,[10][11][12][14][15][16][17][18]25,26]. However, a tremendous number of channels is needed t achieve a high sampling rate.…”

Section: Introductionmentioning

confidence: 99%

A 2.5-GS/s Four-Way-Interleaved Ringamp-Based Pipelined-SAR ADC with Digital Background Calibration in 28-nm CMOS

et al. 2021

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A 2.5-GS/s 12-bit four-way time-interleaved pipelined-SAR ADC is presented in 28-nm CMOS. A bias-enhanced ring amplifier is utilized as the residue amplifier to achieve high bandwidth and excellent power efficiency compared with a traditional operational amplifier. A high linearity front-end is proposed to alleviate the non-linearity of the diode for ESD protection in the input PAD. The embedded input buffer can suppress the kickback noise at high input frequencies. A blind background calibration based on digital-mixing is used to correct the mismatches between channels. Additionally, an optional neural network calibration is also provided. The prototype ADC achieves a low-frequency SNDR/SFDR of 51.0/68.0 dB, translating a competitive FoMw of 0.48 pJ/conv.-step at 250 MHz input running at 2.5 GS/s.

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“…An adjustment scheme is incorporated between differential and common-mode reference voltages for improving the ADC linearity. Using excessive number of comparators in flash ADCs [17]- [20] with higher resolutions lead to high power requirement and integration space.…”

Section: Introductionmentioning

confidence: 99%

Low Power 10-Bit Flash ADC with Divide and Collate Subranging Conversion Scheme

2019

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The sampling rate plays a key role in wireless applications at very high-frequency range. Flash analog-to-digital converter (ADC) betters the slow converter counterparts in this regard but bulky at inevitable high resolutions. A state-of-the-art Divide and Collate (DnC) algorithm is proposed to design the flash ADC at subranging levels. The offset voltage is kept at a minimum through the comparators used for novel coarse and fine conversion separately. The kick-back noise is also reduced by using sample and hold switches at the input. The 10-bit ADC architecture is designed with 45-nm CMOS technology and analyzed in the SPECTRE environment. A trivial variation in the transconductance with temperature is observed and consequently the offset drift with temperature is found to be 0.015 mV/ • C. The design improves the INL by 0.42 LSB and DNL by 0.3 LSB. Signal-tonoise-and-distortion (SNDR) ratio and spurious-free-dynamic-range (SFDR) are 51.8 dB and 62 dB respectively at a frequency range near the Nyquist rate with a supply voltage of 1 V and input frequency of 500 MHz. Subranging scheme minimizes the comparator requirements which is reflected in the 44% reduction in the power dissipation.

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A 40-mW 7-bit 2.2-GS/s Time-Interleaved Subranging CMOS ADC for Low-Power Gigabit Wireless Communications

Cited by 29 publications

References 18 publications

Mismatch calibration methods for high-speed time-interleaved ADCs

Mismatch calibration methods for high-speed time-interleaved ADCs

A 2.5-GS/s Four-Way-Interleaved Ringamp-Based Pipelined-SAR ADC with Digital Background Calibration in 28-nm CMOS

Low Power 10-Bit Flash ADC with Divide and Collate Subranging Conversion Scheme

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