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A 7-bit, 2.6 GS/s time-interleaved analogue-to-digital converter (ADC) for 60 GHz applications is designed and fabricated in 65 nm CMOS. The proposed subranging ADC architecture with time-shifting track-and-hold and two-phase amplification and encoding significantly enhances the speed of individual ADCs and reduces the number of interleaved channels to only four. At 2.6 GS/s sampling rate with a 1.355 GHz input signal, the ADC achieves an effective number of bits of 5.5 bits. Its core occupies 0.3 mm 2 chip area and draws 45 mA current from a 1 V supply.Introduction: High-speed (.1 GS/s), medium resolution (6-8 bits) analogue-to-digital converters (ADCs) with low power consumption and small area are key to 60 GHz CMOS transceivers for high data rate wireless communications. Time-interleaved (TI) ADC architecture, which combines multiple low-speed power-efficient subADCs, is considered an ideal candidate to achieve such specifications and is widely employed in recent developments [1,2]. The time-interleaved ADC, however, suffers from several drawbacks such as large area as the number of channels increases to achieve a high aggregated sampling rate, complicated signal routing, and excessive parasitic of long routing lines that degrade circuit speed. Moreover, significant mismatches among channels can deteriorate ADC linearity performance. All these necessitate circuit design techniques that can reduce the number of interleaved channels and minimise area and power overheads.In this reported work, we designed and implemented a time-interleaved ADC in 65 nm general purpose (GP) CMOS. A novel subranging ADC architecture with significantly higher sampling rate is proposed and serves as the core of each subADC in the time-interleaved ADC. This subranging-based architecture greatly reduces the required channel number while maintaining low power consumption. It results in an ADC with optimum performance in terms of total area and power efficiency compared to the successive-approximation-register (SAR) based [1] or pipelined-based [2] time-interleaved ADCs. In addition, it has been successfully integrated into a 60 GHz CMOS transceiver.