A 40-mW 7-bit 2.2-GS/s time-interleaved subranging ADC for low-power gigabit wireless communications in 65-nm CMOS

Ku, I-Ning; Xu, Zhiwei; Kuan, Yen-Cheng; Wang, Yen-Hsiang; Chang, Mau-Chung Frank

doi:10.1109/cicc.2011.6055328

Cited by 8 publications

(5 citation statements)

References 8 publications

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“…The calibration improves the SNDR from 62.6 dB (10.11 ENOB) to 69.1 dB (11.19 ENOB) and SFDR from 64.2 dB to 81.21 dB. In a conclusion, the timing, offset and gain mismatches are the three important error sources for the time interleaved ADC [10]. Variations between the individual ADCs in a time-interleaved system are the root cause of these three error sources, which may have much greater impact on analog components than digital components.…”

Section: Simulation Results Discussionmentioning

confidence: 96%

A novel redundant pipelined successive approximation register ADC

Fan

Wei

Qiao

et al. 2013

IEICE Electron. Express

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This paper presents a 12-bit 100 MS/s time-interleaved successive approximation register (SAR) ADC designed for intermediate frequency 3G receivers. The 12-bit 100 MS/s 2-channel ADC with voltage-controlled delay lines (VCDLs) based time-domain comparator is designed in 65 nm CMOS, single-channel 12-bit 50 MS/s pipelined SAR ADC consists of a 6-bit MDAC first stage and a 7-bit SAR ADC second stage, the operational amplifier is shared between the two channels for low power dissipation. A novel redundant SAR ADC used in the first stage is proposed to avoid comparator offset issue. Moreover, tri-level flash-SAR ADC is proposed and used in the second stage, the total unit capacitors to realize a 7-bit tri-level flash-SAR ADC are 50% of the conventional two's complement flash-SAR architecture. Simulation results in 65 nm CMOS process show that, the 12-bit 100 MS/s ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 73.32 dB (11.89 ENOB), a spurious free dynamic range (SFDR) of 90.65 dB with a 2.7 MHz input tone, while dissipating 10 mW from a 1.2 V supply.

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Section: Simulation Results Discussionmentioning

confidence: 96%

A novel redundant pipelined successive approximation register ADC

Fan

Wei

Qiao

et al. 2013

IEICE Electron. Express

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“…The performance of the buffered window comparator in the back-end is tabulated in Table 2, illustrating its relative merits with respect to data rate, power dissipation, speed/power ratio, and supply voltage. To quantify the relative simulated performance of the proposed decision block with respect to published detection circuits [39][40][41][42][43][44][45][46][47][48][49], a second figure-of-merit (FOM 2 ) is defined with…”

Section: Isrn Electronicsmentioning

confidence: 99%

High-Gain Power-Efficient Front- and Back-End Designs for a 90 nm Transmit-Reference Receiver

Roy

2012

ISRN Electronics

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A new microwave receiver configuration which transmits reference pulses embedded in data streams for synchronization is analyzed with a 90-nm IBM CMOS standard. A two-stage cascode low-noise amplifier (LNA) is proposed for the receiver front-end which is matched by a passive network to save on power-expensive matching techniques. The amplifier exploits a double-differential topology and achieves a below 4 dB noise figure near the center frequency. The overall 3-dB bandwidth is 3.3 GHz with peaking up to 20.5 dB in the -band. The back-end of the receiver is implemented through an adjustable analog window-detection circuit. It avoids the use of control voltage generators and sample-hold (S/H) blocks to save electronic overhead and is simulated with a 0.1~2.0 Gbps pulse stream. The achieved speed-to-power ratio for the back-end has a maximum limit of 266 GHz/W. When compared against simulated results of published literature, the proposed designs show improved performance in terms of small-signal gain, noise, speed, and power dissipation.

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“…Ultra-wideband (UWB) wireless communication is one of the contributors to the prosperity of the IoT and is also one of the representative beneficiaries that is continuing to evolve with the IoT. With the continued development of UWB wireless communications, the demand for multi-GS/s (giga sample per second) high-speed and medium-resolution analog-to-digital converters (ADCs) have been ever-increasing [5][6][7][8][9][10]. To meet the high-speed requirements, flash ADCs have been the most widely used in UWB applications.…”

Section: Introductionmentioning

confidence: 99%

Time-Interleaved SAR ADC with Background Timing-Skew Calibration for UWB Wireless Communication in IoT Systems

Seong

Jung

Yoon

et al. 2020

Sensors

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Ultra-wideband (UWB) wireless communication is prospering as a powerful partner of the Internet-of-things (IoT). Due to the ongoing development of UWB wireless communications, the demand for high-speed and medium resolution analog-to-digital converters (ADCs) continues to grow. The successive approximation register (SAR) ADCs are the most powerful candidate to meet these demands, attracting both industries and academia. In particular, recent time-interleaved SAR ADCs show that multi-giga sample per second (GS/s) can be achieved by overcoming the challenges of high-speed implementation of existing SAR ADCs. However, there are still critical issues that need to be addressed before the time-interleaved SAR ADCs can be applied in real commercial applications. The most well-known problem is that the time-interleaved SAR ADC architecture requires multiple sub-ADCs, and the mismatches between these sub-ADCs can significantly degrade overall ADC performance. And one of the most difficult mismatches to solve is the sampling timing skew. Recently, research to solve this timing-skew problem has been intensively studied. In this paper, we focus on the cutting-edge timing-skew calibration technique using a window detector. Based on the pros and cons analysis of the existing techniques, we come up with an idea that increases the benefits of the window detector-based timing-skew calibration techniques and minimizes the power and area overheads. Finally, through the continuous development of this idea, we propose a timing-skew calibration technique using a comparator offset-based window detector. To demonstrate the effectiveness of the proposed technique, intensive works were performed, including the design of a 7-bit, 2.5 GS/s 5-channel time-interleaved SAR ADC and various simulations, and the results prove excellent efficacy of signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) of 40.79 dB and 48.97 dB at Nyquist frequency, respectively, while the proposed window detector occupies only 6.5% of the total active area, and consumes 11% of the total power.

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A 40-mW 7-bit 2.2-GS/s time-interleaved subranging ADC for low-power gigabit wireless communications in 65-nm CMOS

Cited by 8 publications

References 8 publications

A novel redundant pipelined successive approximation register ADC

A novel redundant pipelined successive approximation register ADC

High-Gain Power-Efficient Front- and Back-End Designs for a 90 nm Transmit-Reference Receiver

Time-Interleaved SAR ADC with Background Timing-Skew Calibration for UWB Wireless Communication in IoT Systems

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