A 40 nm 512 kb Cross-Point 8 T Pipeline SRAM With Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-Assist

Lien, Nan Chun; Chu, Leiqiang; Chen, Chien Hen; Yang, Hao I.; Tu, Ming Hsien; Kan, Paul Sen; Hu, Yong; Chuang, Ching Te; Jou, Shyh-Jye; Hwang, Wei

doi:10.1109/tcsi.2014.2336531

Cited by 33 publications

(15 citation statements)

References 15 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…As it provides a large signal VTC, it would allow fast switching with large voltage gain. In proposed cells, the PUNs represent the load transistors built with pseudo-nMOS inverter as showjn in Figure 1 To keep the cell area within the reasonable value, the width of the cell ratio is kept in the range given by (1). The stability of the write SNM depends on the pull-up ratio.…”

Section: Read Access Time (Tra) and Stabilitymentioning

confidence: 99%

“…SRAM technology is more suitable for high-speed and low-power applications like processors, computing units and other sophisticated devices, scientific and industrial subsystems, modern appliances, automotive electronics, mobile phones etc [1], [2]. Low-Power, Low-Voltage stability with high packaging density has represented the fundamental topics of the recent decade regarding SRAM outlines [3].…”

Section: Introductionmentioning

confidence: 99%

“…The past industry evolved patterns to investigate the bigger cell and more colorful SRAM hardware styles are in the scaled environments [7]. Some of the existing architectures of SRAM cell are 6T, 7T, 8T, 9T, 10T [1], [3], 11T [5] and 13T [6]. The 6T-SRAM cell suffers from read/write access distribution, scaling, soft errors and stability of the cell diminishes at low-voltage.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Energy optimization of 6T SRAM cell using low-voltage and high-performance inverter structures

Reddy¹,

Sailaja²,

Babulu³

2019

IJECE

View full text Add to dashboard Cite

The performance of the cell deteriorates, when static random access memory (SRAM) cell is operated below 1V supply voltage with continuous scale down of the complementary metal oxide semiconductor (CMOS) technology. The conventional 6T, 8T-SRAM cells suffer writeability and read static noise margins (SNM) at low-voltages leads to degradation of cell stability. To improve the cell stability and reduce the dynamic power dissipation at low- voltages of the SRAM cell, we proposed four SRAM cells based on inverter structures with less energy consumption using voltage divider bias current sink/source inverter and NOR/NAND gate using a pseudo-nMOS inverter. The design and implementation of SRAM cell using proposed inverter structures are compared with standard 6T, 8T and ST-11T SRAM cells for different supply voltages at 22-nm CMOS technology exhibit better performance of the cell. The read/write static noise margin of the cell significantly increases due to voltage divider bias network built with larger cell-ratio during read path. The load capacitance of the cell is reduced with minimized switching transitions of the devices during high-to-low and low- to-high of the pull-up and pull-down networks from VDD to ground leads to on an average 54% of dynamic power consumption. When compared with the existing ones, the read/write power of the proposed cells is reduced to 30%. The static power gets reduced by 24% due to stacking of transistors takes place in the proposed SRAM cells as compare to existing ones. The layout of the proposed cells is drawn at a 45-nm technology, and occupies an area of 1.5 times greater and 1.8 times greater as compared with 6T-SRAM cell.

show abstract

Section: Read Access Time (Tra) and Stabilitymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Energy optimization of 6T SRAM cell using low-voltage and high-performance inverter structures

Reddy¹,

Sailaja²,

Babulu³

2019

IJECE

View full text Add to dashboard Cite

show abstract

“…However, all functions of an SRAM such as read, write and hold margins will be affected by increased process variation at low supply voltages (e.g., near or sub-threshold regions) which has degraded the yield. To improve the performance of the SRAM cell at ultra-low supply voltages, several FinFET SRAM solutions from device level [13] to circuit [17][18][19] and architecture level [20][21][22][23][24] have been proposed. However, most of these architectures suffer from degraded access time, especially at near/sub-threshold regions.…”

Section: Finfet-based Srammentioning

confidence: 99%

Low Power Design for Future Wearable and Implantable Devices

Lundager

Zeinali

Tohidi

et al. 2016

JLPEA

View full text Add to dashboard Cite

With the fast progress in miniaturization of sensors and advances in micromachinery systems, a gate has been opened to the researchers to develop extremely small wearable/implantable microsystems for different applications. However, these devices are reaching not to a physical limit but a power limit, which is a critical limit for further miniaturization to develop smaller and smarter wearable/implantable devices (WIDs), especially for multi-task continuous computing purposes. Developing smaller and smarter devices with more functionality requires larger batteries, which are currently the main power provider for such devices. However, batteries have a fixed energy density, limited lifetime and chemical side effect plus the fact that the total size of the WID is dominated by the battery size. These issues make the design very challenging or even impossible. A promising solution is to design batteryless WIDs scavenging energy from human or environment including but not limited to temperature variations through thermoelectric generator (TEG) devices, body movement through Piezoelectric devices, solar energy through miniature solar cells, radio-frequency (RF) harvesting through antenna etc. However, the energy provided by each of these harvesting mechanisms is very limited and thus cannot be used for complex tasks. Therefore, a more comprehensive solution is the use of different harvesting mechanisms on a single platform providing enough energy for more complex tasks without the need of batteries. In addition to this, complex tasks can be done by designing Integrated Circuits (ICs), as the main core and the most power consuming component of any WID, in an extremely low power mode by lowering the supply voltage utilizing low-voltage design techniques. Having the ICs operational at very low voltages, will enable designing battery-less WIDs for complex tasks, which will be discussed in details throughout this paper. In this paper, a path towards battery-less computing is drawn by looking at device circuit co-design for future system-on-chips (SoCs). dynamic power consumption, which means that a great deal of the power spent, is wasted solely on heat generation [1]. This can be dealt with by further researching cooling and packaging in order to avoid overheating the circuits; however, this is an expensive and time limited solution, so this paper addresses methods to generally reduce the overall power consumption of the systems.Since the Internet of Things (IoT) revolution, a new focus has been made on making smart phones, smart watches, tablets etc. even smaller whilst increasing the computation power. And with the recent interest in the Internet of Bio-Nano Things (IoBNT) [2], the focus has moved from just increasing the computation power to also creating extremely compact, ultra low power designs that enable small sensors and actuators to operate independently of wired data connections and external power sources. Especially for implanted sensors, the size restriction is crucial for the bio-compatibility and therefore, ...

show abstract

“…Besides, in 6 T‐SRAM cell, the conflict between read and write limits the minimum supply voltage; hence, the window of lowering the supply voltage to achieve lower power consumption is reduced further. To improve the performance of the SRAM cell at ultra‐low supply voltages, several FinFET SRAM solutions from device level to circuit and architecture level have been proposed. In , an asymmetric device FinFET is realized by unequally doped drain and source terminals leading to unequal currents flow for positive and negative Drain‐Source (V DS ) voltages.…”

Section: Introductionmentioning

confidence: 99%

Low‐leakage sub‐threshold 9 T‐SRAM cell in 14‐nm FinFET technology

Zeinali

Madsen

Raghavan

et al. 2016

Circuit Theory & Apps

View full text Add to dashboard Cite

Summary A novel sub‐threshold 9 T Static Random Access Memory (SRAM) cell designed and simulated in 14‐nm FinFET technology is proposed in this paper. The proposed 9 T‐SRAM cell offers an improved access time in comparison to the 8 T‐SRAM cell. Furthermore, an assist circuit is proposed by which the leakage current of the proposed SRAM cell is reduced by 20% when holding ‘0’ and an equal leakage current during hold ‘1’ in comparison to the 8 T‐SRAM cell. The proposed circuit improves the access time by 40% in comparison to the 8 T‐SRAM cell without any degradation in write and read noise margins, as well. The maximum operating frequency of the proposed SRAM cell is 1.53 MHz at VDD = 270 mV. Copyright © 2016 John Wiley & Sons, Ltd.

show abstract

A 40 nm 512 kb Cross-Point 8 T Pipeline SRAM With Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-Assist

Cited by 33 publications

References 15 publications

Energy optimization of 6T SRAM cell using low-voltage and high-performance inverter structures

Energy optimization of 6T SRAM cell using low-voltage and high-performance inverter structures

Low Power Design for Future Wearable and Implantable Devices

Low‐leakage sub‐threshold 9 T‐SRAM cell in 14‐nm FinFET technology

Contact Info

Product

Resources

About