A 44-fJ/Conversion Step 200-MS/s Pipeline ADC Employing Current-Mode MDACs

Briseno-Vidrios, Carlos; Zhou, Dadian; Prakash, Suraj; Liu, Qiyuan; Edward, Alexander; Soenen, Eric; Kinyua, Martin; Silva-Martí­nez, J.

doi:10.1109/jssc.2018.2863959

Cited by 15 publications

(4 citation statements)

References 29 publications

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“…6. Silicon area of the OTA is 0.053 mm 2 . The open loop frequency responses are measured using the E5061B network analyzer, and the results are shown in Fig.…”

Section: Simulation and Experimental Resultsmentioning

confidence: 99%

98-dB Gain Class-AB OTA With 100 pF Load Capacitor in 180-nm Digital CMOS Process

et al. 2019

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In this paper, a new two-stage class-AB operational trans-conductance amplifier (OTA) is proposed. Using active loads in the first stage and improved recycling structure, the effective trans-conductance of the first stage is increased. The nonlinear current mirrors boost the current of the second stage in the slewing mode, leading to the increase of the slew rate (SR). Exploiting the multi-path scheme and increasing the effective trans-conductance cause the OTA DC-gain to be enhanced. The proposed OTA has been fabricated using 1P6M 180-nm CMOS technology under 1.8 V supply voltage. The OTA exhibits 98 dB DC-gain and 21 MHz unity-gain bandwidth with a 100 pF capacitive load, consuming 3 mW from 1.8 V supply voltage. INDEX TERMS Class-AB OTA, trans-conductance, nonlinear current mirror, multi-path scheme, DC-gain.

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“…6. Silicon area of the OTA is 0.053 mm 2 . The open loop frequency responses are measured using the E5061B network analyzer, and the results are shown in Fig.…”

Section: Simulation and Experimental Resultsmentioning

confidence: 99%

98-dB Gain Class-AB OTA With 100 pF Load Capacitor in 180-nm Digital CMOS Process

et al. 2019

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“…The ADC output is thermometer-coded and directly controls the fifteen DPTs. The conventional architecture implements each comparator cell: a pre-amplifier, a strong-arm latch, and an SR latch, as described in [30]. The pre-amplifier has an approximate gain of 3 v/v.…”

Section: Flash Adcmentioning

confidence: 99%

A Self-Triggered Digitally Assisted Hybrid LDO with 110 ns Settling Time in 65 nm CMOS

2023

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This article presents a self-triggered digitally assisted hybrid low-dropout regulator (LDO). The proposed architecture uses an analog LDO for steady-state operation and a digital LDO to track large output current changes. The dual loop has a loop controller for coherent operation, and the digital loop is only triggered when there is a large load step. Therefore, the proposed LDO inherits some of the advantages of both parts. It achieves a high power supply rejection ratio (PSRR) from the analog part. The digital loop has a faster settling time and consumes less static power than the analog loop. In this design, the maximum load is 200 mA. For heavy load conditions, PSRR is −40 dB at 1 MHz. The quiescent current is 200 μA. The undershoot/overshoot with the corresponding settling time measured under a load current step of 200 mA/10 ns are 82 mV/89 ns and 112 mV/110 ns, respectively. The proposed LDO achieves a competitive 4.48 ps figure of merit. In the TSMC 65 nm process, the active area is approximately 0.027 mm2.

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“…A negative zero point (-1/Rs Cs) is introduced into the system and the main pole of the original circuit is reduced (from -1/ Zout Cs to -1/ (Zout + Rs) Cs). In order to achieve SNDR improvement and reduce layout area, the value of Cs and Rs not be too small, especially in the former stages of pipelined ADC [32]. Therefore the negative zero will be at a lower frequency.…”

Section: P2mentioning

confidence: 99%

A parasitic elimination bootstrapped switch and a fast settling residual amplifier for high-speed and high-resolution pipelined ADC

Liu¹,

Chen²,

Wang³

et al. 2022

IEICE Electron. Express

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This letter proposes a parasitic elimination bootstrapped switch and a fast settling residual amplifier to be used in multiplying digital-toanalog converter (MDAC) in order to improve the performance of pipelined ADC at high frequency. The parasitic elimination bootstrapped switch improves the sampling spurious free dynamic range (SFDR) by more than 6dB by shielding the nonlinear parasitic capacitance of the MOS transistor substrate. In addition, at high frequency, the negative zero point introduced by the later stage switch-capacitor circuit (which is easy to be ignored) will seriously deteriorates the settling time of residual amplifier in the former stage. A new zero-pole elimination technique is proposed, which greatly reduces the settling time of residual amplifier by nearly 11% and further improve the performance of MDAC. Simulated in 28nm CMOS technology, as the input signal is 1.38GHz, the former stage of the pipelined ADC implements high-speed high-resolution to obtain a SFDR of 75.77dB and a signal-to-noise-plus-distortion ratio (SNDR) of 68.05dB at a sampling frequency of 2.2GS/s.

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A 44-fJ/Conversion Step 200-MS/s Pipeline ADC Employing Current-Mode MDACs

Cited by 15 publications

References 29 publications

98-dB Gain Class-AB OTA With 100 pF Load Capacitor in 180-nm Digital CMOS Process

98-dB Gain Class-AB OTA With 100 pF Load Capacitor in 180-nm Digital CMOS Process

A Self-Triggered Digitally Assisted Hybrid LDO with 110 ns Settling Time in 65 nm CMOS

A parasitic elimination bootstrapped switch and a fast settling residual amplifier for high-speed and high-resolution pipelined ADC

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