A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations

Nii, Koji; Yabuuchi, Makoto; Tsukamoto, Yasumasa; Ohbayashi, S.; Imaoka, Shingi; Makino, Hiroshi; Yamagami, Y.; Ishikura, Satoshi; Terano, T.; Oashi, T.; Hashimoto, Kohei; Sebe, A.; Okazaki, Shoji; Satomi, K.; Akamatsu, H.; Shinohara, Hirofumi

doi:10.1109/jssc.2007.907998

Cited by 57 publications

(18 citation statements)

References 23 publications

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“…Some other techniques to lower the core Vdd voltage include floating the selected write columns [12]; charge sharing between the selected column and an appropriately sized predischarged dummy capacitance to create the lower voltage level [7] etc. The main challenge with this technique is to make sure that the lowered column voltage is still higher than the retention voltage of the unselected bit cells in the same column.…”

Section: Sram Write-ability Metricmentioning

confidence: 99%

On the efficacy of write-assist techniques in low voltage nanoscale SRAMs

Chandra¹,

Pietrzyk²,

Aitken³

2010

2010 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE 2010)

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Read and write assist techniques are now commonly used to lower the minimum operating voltage (Vmin) of an SRAM. In this paper, we review the efficacy of four leading write-assist (WA) techniques and their behavior at lower supply voltages in commercial SRAMs from 65nm, 45nm and 32nm low power technology nodes. In particular, the word-line boosting and negative bit-line WA techniques seem most promising at lower voltages. These two techniques help reduce the value of W Lcrit by a factor of ∼2.5X at 0.7V and also decrease the 3σ spread by ∼3.3X, thus significantly reducing the impact of process variations. These write-assist techniques also impact the dynamic read noise margin (DRNM) of half-selected cells during the write operation. The negative bit-line WA technique has virtually no impact on the DRNM but all other WA techniques degrade the DRNM by 10-15%. In conjunction with the benefit (decrease in W Lcrit) and the negative impact (decrease in DRNM), overhead of implementation in terms of area and performance must be analyzed to choose the best write-assist technique for lowering the SRAM Vmin.

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Section: Sram Write-ability Metricmentioning

confidence: 99%

On the efficacy of write-assist techniques in low voltage nanoscale SRAMs

Chandra¹,

Pietrzyk²,

Aitken³

2010

2010 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE 2010)

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“…Read assist scheme WLUD improves the stability of half-selected bitcells but degrades both the read and write performances of selected bitcell [4]. Further WLUD scheme also shows rise in access time of bitcell with reducing V MIN , then to improve the V MIN , disturbance noise reduction (DNR) scheme was proposed as read assist scheme [2].…”

Section: Proposed Low Power Disturbance Noise Reduction (Lp-dnr) Schemementioning

confidence: 99%

A 28-nm 32Kb SRAM For Low-VMIN Applications Using Write and Read Assist Techniques

Kumar¹,

Saha²,

Gupta³

2017

RADIOENGINEERING

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“…Fig. 20 demonstrates the effectiveness of boosting and under-drive for read assist [17]. boosting was found to provide a larger improvement in critical read stability compared to under-drive.…”

Section: E Impact Of Assist Techniquesmentioning

confidence: 99%

Characterization of Dynamic SRAM Stability in 45 nm CMOS

Toh

Guo

Liu

et al. 2011

IEEE J. Solid-State Circuits

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Abstract-Optimization of SRAM yield using dynamic stability metrics has been evaluated in the past to ensure continued scaling of bitcell size and supply voltage in future technology nodes. Various dynamic stability metrics have been proposed but they have not been used in practical failure analysis and compared with conventional static margins. This work compares static and dynamic metrics to identify expected correlations. A dynamic stability characterization architecture using pulsed word-lines is implemented in 45 nm CMOS to identify sources of variability, and their impact on SRAM stability. Static read margins were observed to overestimate failures by 10-100 X while static write margins failed to predict outliers in critical writeability. Critical writeability was demonstrated to exhibit an enhanced sensitivity to process variations, random telegraph noise (RTN), and negative bias temperature instability (NBTI), compared to static write margins.

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A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations

Cited by 57 publications

References 23 publications

On the efficacy of write-assist techniques in low voltage nanoscale SRAMs

On the efficacy of write-assist techniques in low voltage nanoscale SRAMs

A 28-nm 32Kb SRAM For Low-VMIN Applications Using Write and Read Assist Techniques

Characterization of Dynamic SRAM Stability in 45 nm CMOS

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