A 450 fs 65-nm CMOS Millimeter-Wave Time-to-Digital Converter Using Statistical Element Selection for All-Digital PLLs

Hussein, Ahmed I.; Vasadi, Sriharsha; Paramesh, Jeyanandh

doi:10.1109/jssc.2017.2762698

Cited by 25 publications

(13 citation statements)

References 36 publications

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“…The proposed TDA uses four delay lines with a different delay for creating amplified output. The proposed TDA simulated in 65 nm CMOS process has a small chip size of 0.003 mm 2 and generates a gain of ten with a maximum…”

Section: Resultsmentioning

confidence: 99%

“…Time-to-digital converter (TDC) is a circuit that can measure the time and convert it to the digital code. This circuit has too many applications, such as its use in all-digital phase-locked loop [1][2][3][4], to measure the time difference between the reference and feedback clock and convert this measurement to the digital code for controlling the oscillator.…”

Section: Introductionmentioning

confidence: 99%

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All‐digital delay line‐based time difference amplifier in 65 nm CMOS technology

Razmdideh

Saneei

2019

IET Circuits, Devices & Systems

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Time-to-digital converter (TDC) is one of the important blocks in most of the digital systems that need to have high resolution. Time difference amplifier (TDA) is used in TDC for increasing the resolution. In this study, an all-digital TDA is proposed. The proposed TDA uses the delay lines with difference delay for amplifying. The proposed circuit is designed and simulated in 65 nm CMOS technology and has a gain of ten and a chip area of about 0.003 mm 2. The calculated maximum gain error is 5%. The proposed TDA consumes 0.94 mW power under 1.1 V supply voltage.

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

All‐digital delay line‐based time difference amplifier in 65 nm CMOS technology

Razmdideh

Saneei

2019

IET Circuits, Devices & Systems

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“…Time-to-Digital Converters (TDC) have been extensively used in positron emission tomography (PET) and other experimental physics areas [1]- [3], and in high precision metrology equipment [4]. Current state-of-the-art Application Specific Integrated Circuits (ASIC) TDCs have already achieved precisions in the range of tens of picoseconds [5]- [13]. These advances have been escorted by a strong technological evolution in Field Programmable Gate Arrays (FPGA), which have become a platform of interest for TDC research applications, due to its low cost, fast development cycle and large flexibility.…”

Section: Introductionmentioning

confidence: 99%

Technology Independent ASIC Based Time to Digital Converter

et al. 2020

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This paper proposes a design methodology for a synthesizable, fully digital TDC architecture. The TDC was implemented using a hardware description language (HDL), which improves portability between platforms and technologies and significantly reduces design time. The proposed design flow is fully automated using TCL scripting and standard CAD tools configuration files. The TDC is based on a Tapped Delay Line architecture and explores the use of Structured Data Path (SDP) as a way to improve the TDL linearity by homogenizing the routing and parasitic capacitances across the multiple TDL's steps. The studied approach also secures a stable, temperature independent measurement operation. The proposed TDC architecture was fabricated using TSMC 180nm CMOS process technology, with a 50MHz reference clock and a supply voltage of 1.8V. The fabricated TDC achieved an 111ps RMS resolution and a single-shot precision of 54ps (0.48 LSB) and 279ps (2.51 LSB), with and without post-measurement software calibration, respectively. The DNL across the channel is mostly under 0.3 LSB and a maximum of 8 LSB peak-to-peak INL was achieved, when no calibration is applied.

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“…However, despite the source being common, experimental results of the BTDC prototype show that noise from this setup causes larger SSPs to be measured. This outcome is corroborated by [42]. Hence, the fixed input time difference for the single-shot experiment of the BTDC prototype is generated using the phase shift between two synchronized channels of the AFG.…”

Section: Measurement Resultsmentioning

confidence: 57%

“…A simple method to achieve sub-gate delay TDC time resolution is to replace the simple delay line with a Vernier delay line. This architecture is known as the Vernier delay line TDC [13,27,31,41,42]. Its schematic is shown in Figure 2.5.…”

Section: Vernier Delay Line Tdcmentioning

confidence: 99%

Design of a time-mode analog-to-digital converter utilizing a time-to-digital converter that is scalable with CMOS technology

Teh¹

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I would also like to thank NTU-A*STAR Silicon Technologies Centre of Excellence under Program 11235100003 and MediaTek Singapore for sponsoring the fabrications of the test chips in 0.18 µm and 40 nm CMOS technologies, respectively. In addition, I would like to thank MediaTek Singapore for taking the time to review my projects.Last but not least, I would like to thank my family and friends for their help, support, and encouragement throughout my Ph.D. journey. They are a source of strength during this difficult journey.

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A 450 fs 65-nm CMOS Millimeter-Wave Time-to-Digital Converter Using Statistical Element Selection for All-Digital PLLs

Cited by 25 publications

References 36 publications

All‐digital delay line‐based time difference amplifier in 65 nm CMOS technology

All‐digital delay line‐based time difference amplifier in 65 nm CMOS technology

Technology Independent ASIC Based Time to Digital Converter

Design of a time-mode analog-to-digital converter utilizing a time-to-digital converter that is scalable with CMOS technology

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