A 5.2-GHz cascade-mos 0.35-?m BiCMOS technology ultra-low-power LNA using a novel floating-body method

Abstract

m-wide finger from the Figure 2, however, 0.1-dB larger NF min than that with a 50-m-wide finger. Consequently, a PHEMT of a single unit cell with gate width of 50 m operating at 15% I dss was selected for the amplifier of the first stage. Even with the possible drawback of low IIP value the second stage, the gain stage, was designed with the single unit cell with 25-m wide finger, because the unit cell with 25-m wide finger shows 1.5-dB higher gain than that with 50 m, as revealed in Figure 2. The matching was made with an on-chip inductor at the source for simultaneous noise and gain match by optimizing the series-feedback inductance at the source [5]. Figure 3 shows a schematic diagram and a photograph of the fabricated two-stage MMIC LNA with a chip size of 0.82 ϫ 0.74 mm 2 . This circuit had a major advantage with regard to power reduction because both transistors were connected with a single draincurrent path, which is a current-reusing technology. Due to the characteristic of the circuit topology, this MMIC LNA saved half the power of other two-stage cascade LNAs having two separate current paths. A 5-k⍀ resistor was used to realize the RF block between the gate and DC input. The second stage was loaded with a band-pass LC section so as to increase the gain at 5.8 GHz and the LC network was also used for output matching. Both of the input and output-matching networks satisfied the DC block requirements. PERFORMANCE OF THE FABRICATED LNAThe noise figure and gain of the amplifier were measured on-wafer by using an HP8970B noise-figure meter and an HP8722ES S-parameter network analyzer. The noise figure and gain of the MMIC LNA from 5.4 to 7.0 GHz range are shown in Figure 4. The amplifier achieved a noise figure of 2.55 dB and a gain of 17 dB at 5.8 GHz, respectively. The input and output return losses of the two-stage amplifier were less than Ϫ8 dB between 5.6 and 6.3 GHz, and the LNA had a small signal gain over 15 dB from 5.4 to 7.0 GHz range, as shown in Figure 5. Low DC power dissipation is very important in many portable systems and wireless communication systems where lower power consumption is necessary. When we compared the noise performance and DC power of the two-stage MMIC LNA with state-of-the-art MMIC LNAs using HEMT and PHEMT technology on GaAs, as shown in Figure 6, we achieved superior DC low-power performance along with good noise figure in this work. CONCLUSIONWe have presented a PHEMT MMIC LNA, of which the unit device width and bias condition have been optimized for low power dissipation, while achieving low-noise performance. The fabricated MMIC LNA exhibited a power consumption of 18 mW, a noise figure of 2.55 dB, and a gain of 17 dB at a frequency of 5.8 GHz with a supply voltage of 3 V. ACKNOWLEDGMENTSThis work was financially supported in part by the Ministry of Science and Technology of Korea and KISTEP. Archer, A 2.5-dB low noise 6 to 18 GHz HEMT MMIC amplifier, IEEE

Low-noise amplifiers in wireless communications: state of the art, two new wideband all-active LNAs in SiGe-BiCMOS

“…In no other LNA does the 3 dB bandwidth exceed 3% of the constituent transistor's f T : the RF LNAs in [6,11,16,34,35] have ratios of 0.01, 0.013, 0.027, 0.007 and 0.005, respectively.…”

“…This load is realised using an inductor ( Fig. 2(c); [35]), or using a parallel RC combination [4,16].…”

“…2 Cascode-based LNAs. a Basic cascode [6], b folded cascode [21], c current-reuse cascode [35], d wideband matching [12], e resistive feedback [14], f distributed amplifier [36] Analog Integr Circ Sig Process (2009) 60: 169-193 173 network: combining the cascode configuration with a three-section bandpass-filter based matching ( Fig. 2(d); [12]).…”

A new concept for front‐end circuit integration: From single‐ended antenna to differential‐input connection without any external balun

“…Besides, the proposed circuit is a cascaded two-stage common emitter-source with a current-reused topology for power saving and better figure of merit. More details about the fundamental design concepts for power-saving LNA are also described in [10].…”

Design tradeoff for SiGe 0.35‐μm BiCMOS low‐power and high figure‐of‐merit LNA

“…However, in the CMOS process, the LNA reveals poor NF, whether in cascade two-stage or cascode topology, because the first stage of the LNA, MOS, requires increased power consumption in order to lower the whole circuit noise. Besides, at high frequency, the signal loss through the drain/source to the substrate parasites can severely degrade NF and power gain [5][6][7]. Typically, high-gain and low-noise implementation of LNAs involves high power dissipation, which is not a desirable option with portable wireless systems.…”