A 5.2Gbps HyperTransport¿ Integrated AC Coupled Receiver with DFR DC Restore

Fang, Emerson S.; Asada, G.; Kumar, Ravi; Hale, S.; Leary, Margaret A.

doi:10.1109/vlsic.2007.4342755

Cited by 8 publications

(2 citation statements)

References 1 publication

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“…However, this can increase the chip area. Alternative methods like decision feedback restore 23 and feedforward DC‐coupled method 24 can also be used, but they make the circuit more complex. In some GRS transceivers, AC coupling equalizers produce non‐GRS output signals that do not solve the problems associated with traditional single‐ended signals, such as simultaneous switching noise, signal reference voltage offset, and frequency‐dependent signal return path.…”

Section: Transceiver Circuit Designmentioning

confidence: 99%

A 25‐Gb/s/pin ground‐referenced signaling transceiver with a DC‐coupled equalizer for on‐package communication

Guo,

Chen,

Wang

et al. 2023

Circuit Theory & Apps

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SummaryThis paper proposes a wireline serial link transceiver for on‐package die‐to‐die links based on 12‐nm fin field‐effect transistor (FinFET) technology. The link is crucial for improving the computational performance of larger systems built from chiplets. To achieve high pin/energy efficiency and prevent traditional single‐ended signaling disadvantages, the transceiver adopts single‐ended ground‐reference signaling (GRS) to transfer information. To precompensate for the frequency‐dependent loss, retain the advantages of GRS, and avoid the disadvantages of traditional AC‐coupled equalizer, the transmitter in the transceiver adopts a DC‐coupled switched‐capacitor charge pump equalizer that can transmit GRS and its equilibrium value can be adjusted according to the channel attenuation. This paper proposes a method for timing de‐skew using digital control delay lines to eliminate the timing skew between data and the clock. In addition, this paper presents a duty cycle corrector to avoid duty cycle distortion, with an adjustment range of 44.5% to 52% and a power dissipation of only 30 W. The transceiver has an area of 1.016 0.676 mm2, including one clock lane link and four data lane links. At a nominal 0.8‐V power supply voltage, the aggregate eye‐opening of the measured 25 Gb/s data on an organic substrate channel with an attenuation of −2.2 dB over 6 mm is 0.675 UI, with a bit error rate (BER) of less than 10−12 and an energy efficiency of 1.01 pJ/bit.

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Section: Transceiver Circuit Designmentioning

confidence: 99%

A 25‐Gb/s/pin ground‐referenced signaling transceiver with a DC‐coupled equalizer for on‐package communication

Guo,

Chen,

Wang

et al. 2023

Circuit Theory & Apps

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“…In [24] the authors use decision feedback restore (DFR) circuitry to detect and compensate for CIDs. The block diagram of the architecture is shown in Figure 14.…”

Section: Decision Feedback Restorementioning

confidence: 99%

A Capacitively Coupled, Pseudo Return-to-Zero Input, Latched-Bias Data Receiver

Mathieu

McCue

Duncan

et al. 2018

IEEE J. Solid-State Circuits

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The ever-increasing demand for data throughput from both wired and wireless networks is continuously burdening high-speed chip-to-chip links. With proposed processor-memory interface standards exceeding multiple Tb/s of data [1] and leadingedge data converters requiring tens of Gb/s of data, power and area efficient data transfer is of utmost importance. This work focuses on the development of a small, low-power, fully-integrated, clock-less capacitively-coupled data receiver. The architecture utilizes small on-chip termination and coupling capacitors in order to avoid parasitics, impedance discontinuities and density limitations associated with their board-mounted counterparts. The small coupling capacitors transforms non-return to zero data streams into bi-polar return-to-zero pulse trains. The pulses' polarities are digitally latched into the receiver via input bias switches, generating pseudo return-to-zero (PRZ) waveforms that reduces baseline wander and eliminates the need for data encoding or scrambling. A model of the PRZ signal is vii Vita Oct. 2012 -Feb 2016 ….

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Extending HyperTransport™ technology to 8.0 Gb/s in 32-nm SOI-CMOS processors

Doyle

Loke

Maheshwari

et al. 2011

IEEE Asian Solid-State Circuits Conference 2011

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A 5.2Gbps HyperTransport¿ Integrated AC Coupled Receiver with DFR DC Restore

Cited by 8 publications

References 1 publication

A 25‐Gb/s/pin ground‐referenced signaling transceiver with a DC‐coupled equalizer for on‐package communication

A 25‐Gb/s/pin ground‐referenced signaling transceiver with a DC‐coupled equalizer for on‐package communication

A Capacitively Coupled, Pseudo Return-to-Zero Input, Latched-Bias Data Receiver

Extending HyperTransport™ technology to 8.0 Gb/s in 32-nm SOI-CMOS processors

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A 5.2Gbps HyperTransport¿ Integrated AC Coupled Receiver with DFR DC Restore

Cited by 8 publications

References 1 publication

A 25‐Gb/s/pin ground‐referenced signaling transceiver with a DC‐coupled equalizer for on‐package communication

A 25‐Gb/s/pin ground‐referenced signaling transceiver with a DC‐coupled equalizer for on‐package communication

A Capacitively Coupled, Pseudo Return-to-Zero Input, Latched-Bias Data Receiver

Extending HyperTransport&#x2122; technology to 8.0 Gb/s in 32-nm SOI-CMOS processors

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Extending HyperTransport™ technology to 8.0 Gb/s in 32-nm SOI-CMOS processors