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Recent trends in 5G and radar systems have revealed the need for high-frequency DACs with minimal spurious emissions. Amplitude and timing errors in the DAC have proven to be a significant hindrance to linearity performance and have an increasing impact with frequency. Primary contributors to these errors are impedance mismatches in the current combining network as well as device mismatches.

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The ever-increasing demand for data throughput from both wired and wireless networks is continuously burdening high-speed chip-to-chip links. With proposed processor-memory interface standards exceeding multiple Tb/s of data [1] and leadingedge data converters requiring tens of Gb/s of data, power and area efficient data transfer is of utmost importance. This work focuses on the development of a small, low-power, fully-integrated, clock-less capacitively-coupled data receiver. The architecture utilizes small on-chip termination and coupling capacitors in order to avoid parasitics, impedance discontinuities and density limitations associated with their board-mounted counterparts. The small coupling capacitors transforms non-return to zero data streams into bi-polar return-to-zero pulse trains. The pulses' polarities are digitally latched into the receiver via input bias switches, generating pseudo return-to-zero (PRZ) waveforms that reduces baseline wander and eliminates the need for data encoding or scrambling. A model of the PRZ signal is vii Vita Oct. 2012 -Feb 2016 ….