A 5.6GHz 64kB Dual-Read Data Cache for the POWER6TM Processor

Davis, John D.; Plass, D.; Bunce, P.; Chan, Yiu-Hing; Pelella, A.R.; Joshi, Rajiv V.; Chen, A.; Huott, W.; Knips, T.; Patel, Pramod Kumar; Lo, Kwok-Tung; Fluhr, Eric

doi:10.1109/isscc.2006.1696322

Cited by 16 publications

(8 citation statements)

References 1 publication

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“…The throughput and density of the four methods of implementing RAM storage are compared in Table IV to five high-performance custom SRAMs in 65-nm processes. In this section, we focus on RAMs with one read-write port (which we will refer to as 1rw), as it is a commonly used configuration in larger caches in processors, but some custom CMOS SRAMs have unusual port configurations, such as being able to do two reads or one write [20]. The size column lists the size of the SRAM block.…”

Section: B Sram Blocks (Low Port Count)mentioning

confidence: 99%

Quantifying the Gap Between FPGA and Custom CMOS to Aid Microarchitectural Design

Wong

Betz

Rose

2014

IEEE Trans. VLSI Syst.

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Abstract-This paper compares the delay and area of a comprehensive set of processor building block circuits when implemented on custom CMOS and FPGA substrates, then uses these results to show how soft processor microarchitectures should be different from those of hard processors. We find that the ratios of the custom CMOS versus FPGA area for different building blocks varies considerably more than the speed ratios, thus, area ratios have more impact on microarchitecture choices. Complete processor cores on an FPGA use 17-27× more area ("area ratio") than the same design implemented in custom CMOS. Building blocks with dedicated hardware support on FPGAs such as SRAMs, adders, and multipliers are particularly area-efficient (2-7×), while multiplexers and content-addressable memories (CAM) are particularly area-inefficient (>100×). Applying these results, we find out-of-order soft processors should use physical register file organizations to minimize CAM size.

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Section: B Sram Blocks (Low Port Count)mentioning

confidence: 99%

Quantifying the Gap Between FPGA and Custom CMOS to Aid Microarchitectural Design

Wong

Betz

Rose

2014

IEEE Trans. VLSI Syst.

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“…This translates to leaky and power hungry designs. Dual supply techniques are one way to overcome large leakage, counter process variation and improve cell stability [9]. State-of-the-art memory designs use dual power supplies: a logic power supply, V DD-LOGIC , and a slightly higher SRAM power supply, V CS-SRAM .…”

Section: Vmin and Dual Supply Srammentioning

confidence: 99%

Statistical-aware designs for the nm era

Joshi

Kanj

2009

2009 IEEE International Conference on IC Design and Technology

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As technology scaled beyond the 100nm node, process variation and particularly random variations effects have had significant impact on the design yield. Memory designs, namely SRAMs, have become more prone to fails. Dynamic stability and dynamic noise margins have become a serious concern. Several design methodologies have been proposed to analyze and counter process variations. In this paper, we revisit key variabilitydriven design contributions, in terms of dual supply techniques, bitline clamping methods, and novel circuits with programmable capabilities, with particular emphasis on statistical exploration of the design space.

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“…Other variations use differential NMOS or PMOS domino single-ended sense (see Fig. 2(b)) [4,5]. For two port 6-T SRAM cells, large BL swing sensing by gates is the only option.…”

Section: Sram Sensingmentioning

confidence: 99%