A 5 Gb/s multi-mode transmitter with de-emphasis for PCI Express 2.0/USB 3.0

You, Li; Zhang, Feng; Lv, Junsheng; Zhao, Jian; Qihao, Liu; Zhou, Yumei

doi:10.1007/s10470-014-0397-7

Cited by 3 publications

(2 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…As shown in Figure 6, unlike pre‐emphasis, which boosts the first‐bit level while keeping the levels of other bits constant, or de‐emphasis, which maintains the first‐bit level while lowering the levels of other bits, 25 the TXEQ boosts the level of the first bit while reducing the levels of all bits except for the first bit. This makes the high‐frequency and low‐frequency components of the signal more balanced after high‐frequency attenuation through the transmission link.…”

Section: Transceiver Circuit Designmentioning

confidence: 99%

A 25‐Gb/s/pin ground‐referenced signaling transceiver with a DC‐coupled equalizer for on‐package communication

Guo,

Chen,

Wang

et al. 2023

Circuit Theory & Apps

View full text Add to dashboard Cite

SummaryThis paper proposes a wireline serial link transceiver for on‐package die‐to‐die links based on 12‐nm fin field‐effect transistor (FinFET) technology. The link is crucial for improving the computational performance of larger systems built from chiplets. To achieve high pin/energy efficiency and prevent traditional single‐ended signaling disadvantages, the transceiver adopts single‐ended ground‐reference signaling (GRS) to transfer information. To precompensate for the frequency‐dependent loss, retain the advantages of GRS, and avoid the disadvantages of traditional AC‐coupled equalizer, the transmitter in the transceiver adopts a DC‐coupled switched‐capacitor charge pump equalizer that can transmit GRS and its equilibrium value can be adjusted according to the channel attenuation. This paper proposes a method for timing de‐skew using digital control delay lines to eliminate the timing skew between data and the clock. In addition, this paper presents a duty cycle corrector to avoid duty cycle distortion, with an adjustment range of 44.5% to 52% and a power dissipation of only 30 W. The transceiver has an area of 1.016 0.676 mm2, including one clock lane link and four data lane links. At a nominal 0.8‐V power supply voltage, the aggregate eye‐opening of the measured 25 Gb/s data on an organic substrate channel with an attenuation of −2.2 dB over 6 mm is 0.675 UI, with a bit error rate (BER) of less than 10−12 and an energy efficiency of 1.01 pJ/bit.

show abstract

Section: Transceiver Circuit Designmentioning

confidence: 99%

A 25‐Gb/s/pin ground‐referenced signaling transceiver with a DC‐coupled equalizer for on‐package communication

Guo,

Chen,

Wang

et al. 2023

Circuit Theory & Apps

View full text Add to dashboard Cite

show abstract

“…Current-mode-logic (CML) transmitters and voltage-modelogic (VML) transmitters are frequently used for highspeed data transmission [1,2]. In recent years, VML transmitters have become increasingly popular.…”

Section: Introductionmentioning

confidence: 99%

A 1.89 mW/Gbps SST transmitter with three-tap FFE and impedance calibration

Bai

Zhao

Zuo

et al. 2019

IEICE Electron. Express

Self Cite

View full text Add to dashboard Cite

This study presents an 8 Gbps low-power source-series terminated (SST) transmitter for high-speed serial links. The proposed transmitter consists of a novel hybrid 20:2 multiplexer followed by a three-tap feed-forward equalizer (FFE) and a shunt path SST driver. In addition, a high-precision impedance calibration circuit with slice unit replication is proposed to match the characteristic impedance of channel, whose maximum calibration error is 0.002%. Fabricated in 55-nm CMOS technology and has area of 0.024 mm 2 . Measurement results show that the transmitter achieves data rate of 8 Gbps while maintaining good performance. The transmitter has output swing of 510 mV with −6 dB post-tap equalization, and it consumes 15.1 mW under 1.2 V power supply.

show abstract

A 3.75Gb/s CML output driver with configurable pre-emphasis in 65nm CMOS technology

Wen

Chen

2016

Proceedings of the 2nd International Conference on Communication and Information Processing

View full text Add to dashboard Cite

A 5 Gb/s multi-mode transmitter with de-emphasis for PCI Express 2.0/USB 3.0

Cited by 3 publications

References 8 publications

A 25‐Gb/s/pin ground‐referenced signaling transceiver with a DC‐coupled equalizer for on‐package communication

A 25‐Gb/s/pin ground‐referenced signaling transceiver with a DC‐coupled equalizer for on‐package communication

A 1.89 mW/Gbps SST transmitter with three-tap FFE and impedance calibration

A 3.75Gb/s CML output driver with configurable pre-emphasis in 65nm CMOS technology

Contact Info

Product

Resources

About