A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection

Cho, Sung Yong; Kim, Sung Woo; Choo, Min-Seong; Lee, Jinhyung; Ko, Han-Gon; Jang, Sungchun; Chu, Sang-Hyeok; Bae, Woorham; Kim, Yoonsoo; Jeong, Deog‐Kyoon

doi:10.1109/esscirc.2015.7313908

Cited by 14 publications

(11 citation statements)

References 6 publications

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“…Compared to the ring-type architectures in [1] and [7], it is noticeable that the proposed ILRPLL exhibits a better FoM, even with a large multiplication ratio. …”

Section: Resultsmentioning

confidence: 99%

“…Nonetheless, the design of the pulse generator (PG) producing the suitable injection pulse is challenging [2]. As an alternative to the use of the PG, a complementary switch (CS) injection technique can be employed [7]. However, it is difficult to obtain a large P pp because the injection current flows only during a short transition time.…”

Section: Charge-stored Complementary Switch Injection Techniquementioning

confidence: 99%

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A 285-fs_rmsIntegrated Jitter Injection-Locked Ring PLL with Charge-Stored Complementary Switch Injection Technique

Kim¹,

Jang²,

Cho³

et al. 2016

JSTS:Journal of Semiconductor Technology and Science

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Abstract-An injection-locked ring phase-locked loop (ILRPLL) using a charge-stored complementary switch (CSCS) injection technique is described in this paper. The ILRPLL exhibits a wider lock range compared to other conventional ILRPLLs, owing to the improvement of the injection effect by the proposed CSCS. A frequency calibration loop and a device mismatch calibration loop force the frequency error to be zero to minimize jitter and reference spur.

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“…Compared to the ring-type architectures in [1] and [7], it is noticeable that the proposed ILRPLL exhibits a better FoM, even with a large multiplication ratio. …”

Section: Resultsmentioning

confidence: 99%

Section: Charge-stored Complementary Switch Injection Techniquementioning

confidence: 99%

A 285-fs_rmsIntegrated Jitter Injection-Locked Ring PLL with Charge-Stored Complementary Switch Injection Technique

Kim¹,

Jang²,

Cho³

et al. 2016

JSTS:Journal of Semiconductor Technology and Science

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“…Here to suppress VCO noise DLL is added. This method is referred as injection locking [7,8,9,10]. The first output phase or frequencies are locked to input reference signal using PLL.…”

Section: Fig 3: Output Phase Noise For Silpll [8 10]mentioning

confidence: 99%

“…Reference signal is also injected into SILVCO to further suppress the jitter. Improved PLL Locking reduces Jitter, phase noise and increases locking range [7,8,10]. The phase frequency detector is designed with Clocked Inverter and D Flip Flop using TSPC Logic as shown in The job of M2 is to prevent short circuit between M1, M2 and M5.…”

Section: Fig 3: Output Phase Noise For Silpll [8 10]mentioning

confidence: 99%

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A Low Jitter – Low Phase Noise Wideband Digital Phase Locked Loop In Nanometer Cmos Technology

Patel*,

Naik,

Gandhi

2019

IJRTE

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For high speed communication applications; jitter, phase noise and power consumption are most critical parameters required to be considered for PLL designs. A sub harmonically injection locking concept can be used in PLL to reduce jitter and phase noise. Such design is very effective for high frequency applications. This article presents similar design for 7.5-GHz Phase locked loop in 180 nm CMOS technology. The measured phase noise of the proposed PLL with self aligned injection at 1 MHz offset is 121.14 dBc/Hz and rms jitter is 110 fs. The total dc power consumption is 13.99 mW. To support the claim process variation with design corner analysis using random variations are carried out.

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On advance towards sub-sampling technique in phase locked loops – A review

Tonk

Afzal

2017

Integration

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A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection

Cited by 14 publications

References 6 publications

A 285-fs_rmsIntegrated Jitter Injection-Locked Ring PLL with Charge-Stored Complementary Switch Injection Technique

A 285-fs_rmsIntegrated Jitter Injection-Locked Ring PLL with Charge-Stored Complementary Switch Injection Technique

A Low Jitter – Low Phase Noise Wideband Digital Phase Locked Loop In Nanometer Cmos Technology

On advance towards sub-sampling technique in phase locked loops – A review

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A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection

Cited by 14 publications

References 6 publications

A 285-fsrmsIntegrated Jitter Injection-Locked Ring PLL with Charge-Stored Complementary Switch Injection Technique

A 285-fsrmsIntegrated Jitter Injection-Locked Ring PLL with Charge-Stored Complementary Switch Injection Technique

A Low Jitter – Low Phase Noise Wideband Digital Phase Locked Loop In Nanometer Cmos Technology

On advance towards sub-sampling technique in phase locked loops – A review

Contact Info

Product

Resources

About

A 285-fs_rmsIntegrated Jitter Injection-Locked Ring PLL with Charge-Stored Complementary Switch Injection Technique

A 285-fs_rmsIntegrated Jitter Injection-Locked Ring PLL with Charge-Stored Complementary Switch Injection Technique