In this paper, we present a new voltage-mode biquad filter that uses a six-terminal CMOS fully differential current conveyor (FDCCII). The FDCCII with only 23 transistors in its structure and operating at ± 1.5 V, is based on a class AB fully differential buffer. The proposed filter has the facility to tune gain, ωo and Q. A circuit division circuit (CDC) is employed to digitally control the FDCCII block. This digitally controlled FDCCII is used to realize a new reconfigurable fully-differential integrator and differentiator. We performed SPICE simulations to determine the performance of all circuits using CMOS 0.25 μm technology.

In recent years, perovskite solar cells (PSCs) have been in huge demand because of their ease of production, low cost, flexibility, long diffusion length, lightweight, and higher performance than their counterparts. The PSCs have demonstrated remarkable progress with power conversion efficiency (PCE) up to 25.7% using FAPbI3 as an active layer component. However, lower PCE and device stability restrict PSCs' commercial viability. Further, the photocurrents in PSCs are close to the maximum Shockley–Queisser (SQ) limit. The focus now is on enhancing the open‐circuit voltage and fill factor through modifying charge‐selective contacts, the morphology of perovskite material, and interface modification. The large grain size, uniformity, and coverage area distinguish the crucial factors affecting the PCE of PSCs. Long‐term device stability and degradation mechanisms have also shown significant dependence on the device structure. Therefore, the tailoring of the device structure continues to play a crucial role in the device's performance and stability. In this review, the illustration of the structural development of perovskite solar cells, including advanced interfacial layers and their associated parameters, is discussed in detail. In addition, the challenges that hinder the PSCs' performance are also discussed.

:A rapid growth in semiconductor technology and increasing demand for portable devices powered up by battery has led the manufacturers to scale down the feature size, resulting reduced threshold voltage and thereby enabling integration of extremely complex functionality on a single chip. In CMOS circuits, increased sub-threshold leakage current refers static power dissipation is the result of low threshold voltage. For the most recent CMOS technologies static power dissipation i.e. leakage power dissipation has become a challenging area for VLSI chip designers. According to ITRS (International technology road-map for semiconductors), leakage power is becoming a dominant part of total power consumption. To prolong the battery life of portable devices, leakage power reduction is the primary goal. The main objective of this paper is to present the analysis of leakage components, comprehensive study & analysis of leakage components and to present different proposed leakage power reduction techniques.

No abstract

The design of phase frequency detector (PFD)