A 500-megabyte/s data-rate 4.5 M DRAM

Kushiyama, N.; Ohshima, S.; Stark, D.; Noji, H.; Sakurai, Kazuo; Takase, S.; Furuyama, T.; Barth, R.; Chan, Alan; Dillon, Jeremy; Gasbarro, J.A.; Griffin, M.; Horowitz, Mark; Lee, T.H.; Lee, V.

doi:10.1109/4.210033

Cited by 36 publications

(5 citation statements)

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“…Commonly, in low-latency parallel systems, 3 two receivers are used on each input, one of them triggered by the positive and one by the negative edge of the clock, as Figure 8a shows. Each receiver has 1/2 cycle to sample (while resetting the amplifier).…”

Section: Outmentioning

confidence: 99%

“…Representative receiver designs can achieve bit widths on the order of 4 FO-4, which match the clock limitations. 3,6 Similar to the transmitter, for a higher degree of demultiplexing, designers can employ multiple clock phases with well-controlled spacing. In such a system as Figure 9 shows, the demultiplexing occurs at the input sampling switches.…”

Section: Outmentioning

confidence: 99%

“…Due to cost, these links typically use pseudodifferential signaling. 3,4 In these systems, receivers at each pin share a reference voltage. Reference-voltage sharing creates an imbalance on the load of the reference and input lines.…”

Section: Outmentioning

confidence: 99%

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High-speed electrical signaling: overview and limitations

Yang²,

1998

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A dvances in IC fabrication technology, coupled with aggressive circuit design, have led to exponential growth of IC speed and integration levels. For these improvements to benefit overall system performance, the communication bandwidth between systems and ICs must scale accordingly. Currently, communication links in various applications approach Gbps data rates. These applications include computer-to-peripheral connections, 1 local area networks, 2 memory buses, 3 and multiprocessor interconnection networks. 4 Designers are concerned that these links will soon reach the fundamental limits of electrical signaling. In this article, we examine the limitations of CMOS implementations of highspeed links and show that the links' performance should continue to scale with technology. To handle the interconnects' finite bandwidth, however, requires more sophisticated signaling methods. CMOS circuits, typically slower than circuits implemented in nonmainstream technologies, are particularly attractive for common applications because of their lower cost. The overall system cost is further reduced when signaling components are implemented as macro cells, integrated on the same die with a microprocessor or signal processing block. For this reason, we do not address bipolar or GaAs Gbps links.

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Section: Outmentioning

confidence: 99%

Section: Outmentioning

confidence: 99%

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High-speed electrical signaling: overview and limitations

Yang²,

1998

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“…SRAM has about four times faster random access times, and traditionally consumes the lowest standby power per bit (to below 1 pW/bit [73]). From recent developments, such as synchronous DRAM (SDRAM) using pipelined highspeed data transfer [83][84][85][86], standby power reduction through proper cell biasing techniques and optimized self-refresh timing [74], silicon-on-insulator (SOI) technology [87][88][89], novel dielectric materials [90], new high-speed interfaces [91][92][93]82], variable/dynamic-V T transistor circuits for sub-1-V operation [94][95][96][97], and the increasing value of memorycell density with the advent of the Ôsystem-on-a-chip' [98], it appears that DRAM will remain the memory backbone for future generations of silicon processors.…”

Section: Semiconductor Memorymentioning

confidence: 99%

Tunnelling-based SRAM

Wagt

1999

Nanotechnology

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This paper describes the use of low-current-density tunnelling devices to obtain dense low-power (sub-100 nW/bit) compound semiconductor static random access memory (SRAM); this cell power is over two orders of magnitude lower than the best previously demonstrated in III-V materials. This same circuit topology promises orders of magnitude reduction in static power dissipation for silicon memories, assuming a suitable Si-based negative differential resistance device, at sub-pA current levels, is developed. The concept of low-standby-power tunnelling-based SRAM (TSRAM) is presented in the context of a scaling theory for all memories and a comparison is given across technologies. Experimental results for a 50 nW TSRAM gain cell using ultralow current density (~1 A cm-2) resonant tunnelling diodes and low-leakage heterostructure field-effect transistors are discussed. We describe a one-transistor TSRAM cell, verify its operation, and discuss merits of TSRAM relative to other memory types. Silicon TSRAM standby power is projected to be lower than that of conventional-style silicon SRAM or DRAM.

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“…The above techniques are discussed from the angle of the phase relationship adjustment. According to the synchronization relationship between clocks used to sample data locally and clocks used to generate data at transmitters, the clocking strategies can also be classified into (1) system or global clocking [4,6,11], where the reference clock is shared by both sides; (2) source synchronous/forwarded clocking [3,9,10,12,13], where a clock is fed from transmitters along data channels; (3) embedded clocking [7,8,22], where a clock is embedded into data at the transmitter, and then is extracted at the receiver; (4) local clocking [20,21,[24][25][26][27][28][29][30][31][32][33][34], where clocks are synthesized locally. (1) ~ (3) belong to synchronous, or mesochronous clocking strategies, which is applicable to applications A ~ C, and almost all of conventional CDR (clock and data recovery) techniques can be used; whereas (4) belongs to plesiochronous one, which is preferable to application C, and PI/PS (phase interpolation/ phase selection) type and blind-oversampling (blindoversampling) techniques are usually used [2,35].…”

Section: Conventional Clocking Strategiesmentioning

confidence: 99%

Multi-channel 5Gb/s/ch SERDES with Emphasis on Integrated Novel Clocking Strategies

Zhang¹,

Li²,

Wang³

et al. 2013

JSTS:Journal of Semiconductor Technology and Science

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Abstract-Two novel clocking strategies for a highspeed multi-channel serializer-deserializer (SERDES) are proposed in this paper. Both of the clocking strategies are based on groups, which facilitate flexibility and expansibility of the SERDES. One clocking strategy is applicable to moderate parallel I/O cases, such as high density, short distance, consistent media, high temperature variation, which is used for the serializer array. Each group within the strategy consists of a full-rate phase-locked loop (PLL), a full-rate delay-locked loop (DLL), and two fixed phase alignment (FPA) techniques. The other is applicable to more awful I/O cases such as higher speed, longer distance, inconsistent media, serious crosstalk, which is used for the deserializer array. Each group within the strategy is composed of a PLL and two DLLs. Moreover, a half-rate version is chosen to realize the desired function of 1:2 deserializer. Based on the proposed clocking strategies, two representative ICs for each group of SERDES are designed and fabricated in a standard 0.18 µm CMOS technology. Measurement results indicate that the two SERDES ICs can work properly accompanied with their corresponding clocking strategies.

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A 500-megabyte/s data-rate 4.5 M DRAM

Cited by 36 publications

References 1 publication

High-speed electrical signaling: overview and limitations

High-speed electrical signaling: overview and limitations

Tunnelling-based SRAM

Multi-channel 5Gb/s/ch SERDES with Emphasis on Integrated Novel Clocking Strategies

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