A 500-MHz–1.25-GHz Fast-Locking Pulsewidth Control Loop With Presettable Duty Cycle

Abstract

A 500-MHz-1.25-GHz fast-locking pulsewidth control loop (PWCL) with presettable duty cycle is realized in 0.35-m CMOS technology. The proposed voltage-difference-to-digital converter and switched charge pump circuits reduce the lock time of a conventional PWCL. Compared with the conventional PWCL, the proposed circuit can reduce the lock time by a factor of 2.58. A method to preset the duty cycle of the output clock is also described. Circuit measurements verify that the duty cycle of the output clock can be adjusted from 35% to 70% in steps of 5%.Index Terms-Duty-cycle presetting, fast locking, pulsewidth control loop (PWCL), switched charge pump, voltage-difference-to-digital converter.

Design and Analysis of Asynchronous Sampling Duty Cycle Corrector

“…However, typical duty cycle correctors occupy large areas due to their complicated structures and various component circuits, such as comparators, encoders and decoders, capacitors in the low-pass filter, or finite state machines (FSM) [1][2][3][4][5][6][7][8][9][10][11][12][13]. Therefore, it is strongly advised to implement a duty cycle corrector that consumes a small area.…”

Pulsewidth control loop with a frequency detector for wide frequency range operation

“…To have a clock with 50% duty cycle, several duty cycle correctors (DCCs) [1][2][3][4][5][6] have been presented. The low voltage PWCL [2] uses low supply voltage and fast locking, but the low voltage PWCL needs an exact 50% duty cycle as a reference clock.…”

“…And the preset output clock has a large duty cycle error. The mutual correlated PWCL [3] using a single to complementary circuits to resist the PVT variation does not need exact 50% input clock. The single path PWCL [5] integrates fast locking PWCL and delay-locked loop (DLL) to achieve phase align with the input clock and presets the duty cycle of the clock duty cycle.…”

An Infinite Phase Shift Delay-Locked Loop With Voltage-Controlled Sawtooth Delay Line

“…The wide phase shift is achieved, but the phase discontinuity may occur at the quadrant boundaries. To correct the duty cycle distortion of the clock caused by the VCDL and PVT variations, the pulsewidth control loop (PWCL) [10], [11] or the duty-cycle corrector [2], [12], [13] are usually used in the DLL.…”