2008
DOI: 10.1109/jssc.2008.2004532
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An Infinite Phase Shift Delay-Locked Loop With Voltage-Controlled Sawtooth Delay Line

Abstract: A wide-range delay-locked loop (DLL) with infinite phase shift and digital-controlled duty cycle is presented. By changing the polarity of the input clock of the voltage-controlled sawtooth delay, this proposed DLL achieves infinite phase shift by only a single loop. The proposed DLL has been fabricated in a 0.18 m CMOS process and the core area is 0.45 0.3 mm 2 . The measurement results show the proposed DLL operates from 50 to 500 MHz. The duty cycle of the output clock can be adjusted from 30% to 60% in the… Show more

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Cited by 19 publications
(3 citation statements)
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“…Hence, the deployed ten-stage current starved inverter (buffer) topologybased VCDL has the resolution of 0.22 ns with the edge misalignment of 28.3 ps at 1.8 V supply voltage, and across the 27 o C temperature. The selected ten-stage VCDL resolution is sufficiently high enough, which provides the optimum edge alignment and covers higher frequency range of SILVCO (sub-harmonically injection locked VCO) without significantly degrading the wide band phase noise [38], [40]. Nonetheless, if the number of stages of the deployed VCDL in the proposed architecture is increased above ten for getting the more VCDL resolution, it will lead to more accurate edge alignment, however, at the cost of significant degradation in wide band phase noise [38], [40].…”
Section: Clock-generation and Voltage Control Delay Line (Vcdl)mentioning
confidence: 99%
See 1 more Smart Citation
“…Hence, the deployed ten-stage current starved inverter (buffer) topologybased VCDL has the resolution of 0.22 ns with the edge misalignment of 28.3 ps at 1.8 V supply voltage, and across the 27 o C temperature. The selected ten-stage VCDL resolution is sufficiently high enough, which provides the optimum edge alignment and covers higher frequency range of SILVCO (sub-harmonically injection locked VCO) without significantly degrading the wide band phase noise [38], [40]. Nonetheless, if the number of stages of the deployed VCDL in the proposed architecture is increased above ten for getting the more VCDL resolution, it will lead to more accurate edge alignment, however, at the cost of significant degradation in wide band phase noise [38], [40].…”
Section: Clock-generation and Voltage Control Delay Line (Vcdl)mentioning
confidence: 99%
“…The selected ten-stage VCDL resolution is sufficiently high enough, which provides the optimum edge alignment and covers higher frequency range of SILVCO (sub-harmonically injection locked VCO) without significantly degrading the wide band phase noise [38], [40]. Nonetheless, if the number of stages of the deployed VCDL in the proposed architecture is increased above ten for getting the more VCDL resolution, it will lead to more accurate edge alignment, however, at the cost of significant degradation in wide band phase noise [38], [40]. However, the variation in edge alignment across the voltage and temperature corner ranging from (0 -50 o C) and (1.7 V -1.9 V), is as shown in Fig.…”
Section: Clock-generation and Voltage Control Delay Line (Vcdl)mentioning
confidence: 99%
“…[1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16] Furthermore, in resource sharing applications when a single hardware is scheduled for several operations multiphase clock generation is required. For example, three phases of analog comparators within°ash ADCs, reset, pre-ampli¯cation and latch, can be scheduled in a single stage hardware applying proper timing strategy.…”
Section: Introductionmentioning
confidence: 99%